• State Accepted Answer
  • +1 person also asked this people also asked this
  • Replies 10 replies
  • Subscribers 141 subscribers
  • Views 13431 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?

Cortex M0 internal Failure solution for ALU, CPU and Register rong results

Shashi Bhushan85

Hello All,

I am using Cortex M0 based controller and want to know if the following issues can happen and what can be the possible solution by software to handle the issues:

1. ALU resulting wrong result run time.

2. Register access giving wrong results run time

3. Memory access (RAM or ROM) giving wrong results run time.

Thanks in advance!!

Parents
  • +1 in reply to Shashi Bhushan

    Hi,

    please let us know the resources which you have.

    Do you have Cortex-M0 RTL, don't you?

    Is it a soft macro, isn't it?

    Is your plan is to make MCU with the Cortex-M0 RTL and the other IPs?

    Are the layout carried out by yourself?

    If the above assumption was true, you could a Dual/Tripple-Modular Redundancy Flip-Flops and Memory Wrapper which had ECC scheme in.

    Otherwise, you could make the lock-step configuration for the Cortex-M0.

    Best regards,

    Yasuhiko Koumoto.

Reply
  • +1 in reply to Shashi Bhushan

    Hi,

    please let us know the resources which you have.

    Do you have Cortex-M0 RTL, don't you?

    Is it a soft macro, isn't it?

    Is your plan is to make MCU with the Cortex-M0 RTL and the other IPs?

    Are the layout carried out by yourself?

    If the above assumption was true, you could a Dual/Tripple-Modular Redundancy Flip-Flops and Memory Wrapper which had ECC scheme in.

    Otherwise, you could make the lock-step configuration for the Cortex-M0.

    Best regards,

    Yasuhiko Koumoto.

Children