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Hi all,
I need some clarification related to acknowledge register in GICv3&4 document.
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8.13.11 GICC_IAR, CPU Interface Interrupt Acknowledge Register:
-->In GIC implementations that support two Security states, if the highest priority pending interrupt is
in Group 0, Non-secure reads return the special INTID 1023.
in Group 1, Secure reads return the special INTID 1022.
highest pending priority interrupt -- HPPI (abbreviated by me for convenience).
Group 0 -- G0
Group 1 -- G1
Doubt:
In the above given statements it is said that if HPPI is G1, secure read returns INTID 1022..
Q1) If HPPI is G1 and if Non-Secure read is made to register, Does this register(GICC_IAR) return the valid INTID..?
Q2) If answer is YES to above question then, in what scenario do we use GICC_AIAR register.?
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8.13.4 GICC_AIAR, CPU Interface Aliased Interrupt Acknowledge Register
The GICC_AIAR characteristics are:
Purpose
Provides the INTID of the signaled Group 1 interrupt. A read of this register by the PE acts as an
acknowledge for the interrupt.
In document it is mentioned that we can access this register either in secure/Non-Secure mode.
Q3) Does this register return valid INTID on accessing it through Secure read
Above mentioned questions are as per my understanding, please correct me if i am wrong.
I will be very happy if you can give me clear explanation related this register operation.
Thanks,
Rakesh.
Hi,
Thank you Ash Wilding for kind reply..,
it is very clear.