For example, the codes are executed in core0.
codes:
(1) send SGI to core1 ICC_SGI1R_EL1
(2) set(a) = 1
i) Then the core1 will first see the irq or the change of variable a?
ii) If I add ISB between (1) and (2), what happended?
iii) If I add DMB (read and write)between (1) and (2), what happended?
iv) If I add DSB (read and write)between (1) and (2), what happended?
After I tested, it seems that only iv) which add DSB makes core1 see (2) after (1).
I had checked the discription of DSB, I don't think any rules match this.
Any help will be appreciated. Thanks!
I am such uncertain about what I said after I rethink this several times.
"Architectural execution of a DSB instruction guarantees that:
The last value written to ICC_SGI0R_EL1 or ICC_SGI1R_EL1 is observed by the associated Redistributor."
This sentense means DSB will wait until the "ICC_SGI1R_EL1 is observed by the associated Redistributor".
Is this necesary in SMP? I think maybe not. One core doesn't need to wait this to be happen before it does next thing.
Do you agree?
I am such confused on this kind of issue!!!
Well, yes. It is kinda confusing. I was thinking myself if there is a situation where this is needed. But I did not find a scenario.So, one core writes ICC_SGI0R_EL1, the write will be delayed due to some pipeline, store-buffering effect. Now this core does something which a) either disturbs the previous write or b) depends on this write going through.For (a), I cannot find something.
For (b), neither .. :(