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Hi,
I tested SGI interrupt latency, it seems that GIC3.0's SGI interrupt latency are much bigger than GIC2.0.
How to test:
GIC3.0:
1. read timestamp(t01)
2. core0 write ICC_SGI0R_EL1 to trigger core1, read timestamp(t02)
3. isr in core1, read timestamp(t03)
GIC2.0:
1. read timestamp(t11)
2. core0 write GICD_SGIR to trigger core1, read timestamp(t12)
3. isr in core1, read timestamp(t13)
Result is (had think about the time of reading timestamp):
1. (t02 - t01) nearly 3 times bigger than (t12 - t11) which means system register cost more time than access to memory mapped memory.
2. (t03 - t02) nearly 2 times bigger than (t13 - t12) which means interrupt latency of GIC3.0 are much bigger than GIC 2.0
Is this normal? Any help will be appreciated! Thanks!
BR,
Peng
I tried it on a Zynq US+, but this is a GIC V2 as I see now. I got 0.29us from trigger to IS-process.
I have an i.MX8 on desk, but NXP is not clear which GIC they use: They write about v4 and v3?!
You can check GICD_PIDR2 register.
GICD_PIDR2 bits [7:4] ArchRev will tell whether it is v3 or v4 or v2.
By the way, what timer did you use for counting?
I used the generic timer (CNTPCNT_EL0) running at 100MHz.
Did you have any new test results?
Sorry, no. I have to make a BSP first for the i.MX8.