Scenario:
Sent a buffer reference and its size from EL1 secure world as a SIP SMC, such that EL3 write on that buffer and ERET to EL1.
Query:
1. Does cache flush is required at any exception level to correct read the buffer at EL1 after ERET ?
2. If Yes, Why?
3. If no, then where to fetch related information that explains in detail why it is not required.
For data cache, you must use the DMB or DSB to ensure all explicit memory accesses are observed in order globally.
If it is single core, it doesn't matter whether the memory access is done in EL3 or EL1
If it is multiple cores, the memory access order matters. When Core 0 writes data cache in EL3, before it returns to EL1, core 1 may access that memory.
For instruction cache, ERET from EL3 to EL1 can guarantee that the context switching operation is observed in order.