Hi,
I am doing a writel to a PCIe device which is taking around 3msec due to link in low power state.
writel translates to wmb followed by STR asm instruction.
My question is, while ARM performing STR instruction on CPUx, can any IRQ able to preempt this and run?
Or IRQ can only be performed after this STR instruction is finished?
Thanks,
Shankar
I don't know much of this area, but I though you got an error back saying the device is disabled or powered down so the STR fails.
No I have not got any error for STR.
But wanted to know if STR instruction is taking more machine cycles, can it be pre-emptible from any ISR.
I think it should be possible if the device says to retry instead of fail and the store just retries until it succeeds. Devices can respond with retry to say they will take a while so the bus doesn't get clogged up.
However I've never looking into this and whether this happens and whether one can depend on it being okay when a store to a device is buffered or whether one needs to say strongly ordered or whether it simply doesn't work with current processors is something I don't know. I don't see any really big problems even with buffered stores provided it is marked as device memory but that might be a failure of my imagination. Plus of course the PCIe would have to send back the retry response when it wasn't yet powered up and then start powering up.
I'm surprised no-one has peeped up yet who does know about this - maybe you need to say AMBA and interrupt in a tag and that might get someone. Or specify more precisely the processor.
Thanks, let me see if any PCIe/Interrupt controller expert responds.