Hello,
I have used DS-5+DSTREAM to connect to the A57/A53 big.LITTLE clusters on my Juno dev board. I use the startup_ARMv8_GICv2 example project included with DS-5 as the bare-metal image to run.
When I navigate to the cache view window in DS-5, I can see into the L2 on the A57, but not on the A53. Attached are screenshots showing this behavior.
Is this intentional? Is it possible to see into the A53s' L2? If so, how?
Thank you,
Marc
Hi Matt,
I also think this could be better documented. Specially because the Juno Board SoC comes with two clusters: A53 and A57. While I can look into the A57's L2 cache, I can't look into A53's cache. This differences could be better marked.
Leandro.