Hello,
I have used DS-5+DSTREAM to connect to the A57/A53 big.LITTLE clusters on my Juno dev board. I use the startup_ARMv8_GICv2 example project included with DS-5 as the bare-metal image to run.
When I navigate to the cache view window in DS-5, I can see into the L2 on the A57, but not on the A53. Attached are screenshots showing this behavior.
Is this intentional? Is it possible to see into the A53s' L2? If so, how?
Thank you,
Marc
Hi Marc,
Which version of DS-5 are you using?
Ta,
Matt
Hi Matt,
Thanks for the quick reply. I'm using:
Version: 5.25.0
Build number: 5250010
EDIT: I just saw a new version of DS-5 was released a few days ago. I've updated to:
Version: 5.26.0
Build number: 5260008
But the functionality is still missing.
Oops, might have lead you on a merry path there, when I clicked the A57 image I saw the same thing (no L2 present) which was odd.
The issue here is that isn't any access to the L2 RAMs on Cortex-A53. This isn't a limitation of DS-5 - it's a limitation of the Cortex-A53.
is this limitation of the Cortex-A53 documented anywhere? I couldn't find it.
It's not documented because it doesn't exist.. most companies tend not to dedicate chapters of technical reference manuals on discussion of non-existent features.
You might note that the Cortex-A53 TRM does mention internal RAM access for the L1 cache subsystem, but not for L2. Unfortunately that's a big a clue as you'll get..
(To clarify, the poster above is not me.)
I am disappointed to hear that I cannot debug the L2 cache on the A53.
Obviously there is no expectation to dedicate chapters to non-existent features, but I would have really appreciated knowing about this before purchasing the DSTREAM. Perhaps it was my own fault for not doing enough due diligence, but I was expecting the official ARM debugger to let me debug everything the official ARMv8 dev platform shipped with. I just wish this missing functionality was made clear instead of leaving just a clue...
Thanks for your help.
I also think this could be better documented. Specially because the Juno Board SoC comes with two clusters: A53 and A57. While I can look into the A57's L2 cache, I can't look into A53's cache. This differences could be better marked.
Leandro.
marc (and lrl),
Perhaps it was my own fault for not doing enough due diligence, but I was expecting the official ARM debugger to let me debug everything the official ARMv8 dev platform shipped with. I just wish this missing functionality was made clear instead of leaving just a clue...
Again, it's not a problem with the debugger. There is literally no method available within the Cortex-A53 implementation - not just in Juno, but all possible configurations and designs containing a Cortex-A53 - to access L2 internal RAM via debug registers.
Quite a lot of ARM documentation is written from the perspective of the expectation of a 'certain level of knowledge' on subjects. When we advertise that you can inspect L2 cache contents, we obviously assume you know that this would never be possible on the Cortex-A53 because there's physically no way to do it that is defined by the ARM Architecture or the Cortex-A53 implementation. While some vendors may have left intentional 'backdoors' into the L2 RAMs (for the purposes of things like MBIST) which could be used, these aren't guaranteed, nor guaranteed to be functional in a running system, and obviously down to the SoC vendor.
The difference is adequately marked in the technical references for the Cortex-A53 in as much as it's complete absence from the documentation is a clear indicator that it does not exist and is not possible.
There is nothing architectural (i.e. "must be present in all ARMv8 cores") about internal RAM access, and implementations (both Cortex-A?? and architectural licensee products) may also needfully differ. The lack of presence of this interface on the Cortex-A53 is due to the design of the L2 cache itself (it is designed to be configured out of designs that do not need L2). Correspondingly it's easier to guarantee that it will exist on the Cortex-A57 since it is NOT possible to configure a Cortex-A57 without L2 cache.
It's definitely documented as part of DS-5, in that "Cache awareness is dependent on the exact device and connection method," although we don't document the debugger from a CPU-specific perspective since that would be redundant - it's documented as part of the processor TRM.
Where DS-5 supports specific features of a particular processor (or not) is sometimes documented in the release notes as the features are introduced.
Thanks for the explanation.