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Physical counter in juno board

Gowthami

Hey,

Reading CNTPCT and system counter in different cores results in different results. These values should be common across all the cores. Why is the difference?

Thanks,

Gowthami

  • +1 Arm Employee Badge

    Hi,

    Based on the information provided, I don't know why. I'd expect to see the same value from all the cores too.

    If you can provide some more detailed information about how you are observing this behaviour, someone might be able to suggest something. For example:

    • How are you reading these values (Debugger, SW loop, etc)?
    • Exactly which System Register are you reading (Architectural name or Instruction, there are various subsets of count registers)
    • What EL (Execution Level, EL3, EL2, EL1, EL0)  and Execution State (AArch64 vs AArch32) are you reading it at?
    • What specific (different) values do you see across the cores?

    Regards

    MarkN.

  • 0 Arm Employee Badge in reply to Mark Nicholson

    Curiosity forced me to try this in DS-5, with Linux booted on a Juno board. [All cores are halted in debug state at EL1 Non Secure, AArch64].

    When I refresh debugger's register view I can see CNTPCT_EL0 reflecting the incrementing System Timer. I see the same values reflected in all core's registers (or at least as close to the same as the delay in refreshing one view after another) will allow.

    So reassuringly this test matches the expected behaviour.

  • 0 Arm Employee Badge in reply to Gowthami

    Hi,

    That's confusing, it's not what I see on my board.

    Although you haven't said what the magnitude of the difference is that's concerning you.

    A couple of thoughts:

    • Although the System Timer count is based on a common timebase, the architecture allows for some flexibility (latency when reading via different observers/mechanisms) as long as time can't be seen to go backwards. So I wouldn't necessarily expect to see the same count in such a test, just similar counts.
    • Note the debugger will read the register once on entry to debug state and effectively show a "cached" value. You need to manually refresh the view it to get an updated reading.
  • 0 in reply to Mark Nicholson

    Hi Mark,

    I tried reading the values in DS-5.

    Reading CNTPCT_EL0 register in EL2 (Hypervisor mode) in AArch64 state results in this value. Also, I observed a similar behaviour when I read the memory mapped CNTCV value (0x2a800000).

    Secondary core reports a lower value than the primary core as time goes by.

    Thanks,

    Gowthami