Hi Everyone,
We just bought a Juno Versatile Express board for development. Using the getting started guides and I have successfully installed DS-5 on a host and a rootfs on the board. I'm using the LAMP image provided by Linaro for use with the Juno board (linaro-image-lamp-genericarmv8-20150618-754.rootfs.tar.gz). To set up and test CoreSight I am using the guide provided (On-Target Trace Using the CoreSight Access Library | ARM DS-5 Development Studio) and the readmes provided within the CoreSight_access example source.
Building is no problem but I have two issues:
1. When trying to disable the cpuidle I find that I have no cpuidle directory in any /sys/devices/system/cpu/cpu$ folder.
2. When attempting to run the tracedemo example (rel or dbg) I receive a "CSREG: Failed to detect the board!" error. The Juno r1 is defined in the source as a supported board (and also mentioned in the readme as supported).
Does anyone have an idea why I would be seeing this error?
Thanks in advance for any insight you can provide on CoreSight!
Steve
From <DS-5>/examples/CoreSight_Access_Library.zip/DS-5Examples/CoreSight_access/demos/cs_demo_known_boards.c:
const struct board known_boards[] = { { .do_registration = do_registration_arndale, .n_cpu = 2, .hardware = "ARNDALE", }, { .do_registration = do_registration_tc2, .n_cpu = 5, .hardware = "ARM-Versatile Express", }, { .do_registration = do_registration_juno, .n_cpu = 6, .hardware = "Juno", }, { .do_registration = do_registration_altera, .n_cpu = 2, .hardware = "Altera SOCFPGA", }, { .do_registration = do_registration_snowball, .n_cpu = 2, .hardware = "ST-Ericsson Snowball platform", }, { .do_registration = do_registration_axx5500, .n_cpu = 16, .hardware = "LSI Axxia", }, {} };
The Xilinx Zybo board is not listed as a known board and therefore is not supported.