Hi Everyone,
We just bought a Juno Versatile Express board for development. Using the getting started guides and I have successfully installed DS-5 on a host and a rootfs on the board. I'm using the LAMP image provided by Linaro for use with the Juno board (linaro-image-lamp-genericarmv8-20150618-754.rootfs.tar.gz). To set up and test CoreSight I am using the guide provided (On-Target Trace Using the CoreSight Access Library | ARM DS-5 Development Studio) and the readmes provided within the CoreSight_access example source.
Building is no problem but I have two issues:
1. When trying to disable the cpuidle I find that I have no cpuidle directory in any /sys/devices/system/cpu/cpu$ folder.
2. When attempting to run the tracedemo example (rel or dbg) I receive a "CSREG: Failed to detect the board!" error. The Juno r1 is defined in the source as a supported board (and also mentioned in the readme as supported).
Does anyone have an idea why I would be seeing this error?
Thanks in advance for any insight you can provide on CoreSight!
Steve
Hi Steve,
I am not sure where you found the link to the LAMP image that you are using. You appear to be using the generic armv8 file system, rather than one developed for Juno.
The latest Juno Getting started guide and our Juno Software Guide recommend that you get the latest Linaro Platforms images from Linaro Releases. Here you will find a link to the latest firmware and filesystem binaries developed for Juno and Versatile Express. Please try the Juno software stacks at this location and see how you get on.
Kind regards
Michele
Thanks Michele!
Using the images you pointed at I am able to resolve my cpuidle issue. However I am still experiencing the "CSREG: Failed to detect the board!" error.
Using the ARM Development Platform Software guide I upgraded the boards firmware and kernel using the latest prebuilt binaries (from section 2.7 of the guide): juno-latest-oe-uefi.zip. Next I used the prebuilt LAMP image (from section 2.3 of the guide): lt-vexpress64-openembedded_lamp-armv8-gcc-4.9_20150620-722.img.gz.
After extracting I installed the image on a USB stick using the command:
$ sudo dd if=lt-vexpress64-openembedded_lamp-armv8-gcc-4.9_20150620-722.img of=/dev/sdb
This created a boot and rootfs partition on the drive.
Starting the Juno board with the USB stick attached brought me to a root prompt for the rootfs. I then copied the CoreSight_access example to the board and began to build the example using the readmes provided. The steps I took to build the example are:
# cd CoreSight_access/build/
# make LPAE=1 VA64=1
# cd ../demos/
I did not rebuild the kernel with the recommended setting (That will be my next step after recognizing the board). My current setup is:
# zgrep "CONFIG_STRICT_DEVMEM" /proc/config.gz
CONFIG_STRICT_DEVMEM=y
# zgrep "CONFIG_DEVKMEM" /proc/config.gz
# CONFIG_DEVKMEM is not set
# zgrep "CONFIG_DEBUG_INFO" /proc/config.gz
CONFIG_DEBUG_INFO=y
# CONFIG_DEBUG_INFO_REDUCED is not set
# CONFIG_DEBUG_INFO_SPLIT is not set
# CONFIG_DEBUG_INFO_DWARF4 is not set
I did do the additional configuration for the Juno board. Cpuidle is turned off and the debug hardware is correctly powered.
When I attempt run the program this is the output I see:
# cd ../bin/rel/
# ./tracedemo
Default configuration, no CPU affinity selected. ITM disabled.
kernel symbol found @ 0xFFFFFFC000082000
CoreSight demonstrator
** Currently affine CPUs: #0 #1 #2 #3 #4 #5
CSREG: Failed to detect the board!
From the documentation, source, and readmes the Juno ARMv8 development board should be supported. Would you have any ideas why I would be seeing this error? I have tried it will both the latest OE LAMP image and the Ubuntu image found here: ARM/Juno/Ubuntu - Linaro Wiki. Both result in the same error.
Any help would greatly appreciated!
Hi,
I've just gone through this myself. I get slightly different error messages between Juno R0 and R1, but either way it doesn't seem to be working:
// R0 error message ~/DS-5Examples/CoreSight_access/bin/rel# ./tracedemo Default configuration, no CPU affinity selected. ITM disabled. kernel symbol found @ 0xFFFFFFC000082000 CoreSight demonstrator ** Currently affine CPUs: #0 #1 #2 #3 #4 #5 CSREG: Failed to detect the board!
// R0 error message
~/DS-5Examples/CoreSight_access/bin/rel# ./tracedemo
// R1 error message ~/DS-5Examples/CoreSight_access/bin/rel# ./tracedemo Default configuration, no CPU affinity selected. ITM disabled. kernel symbol found @ 0xFFFFFFC000081000 CoreSight demonstrator ** Currently affine CPUs: #0 #1 #2 #3 #4 #5 CSREG: Board 'ARM Juno development board' not known CSREG: Failed to detect the board!
// R1 error message
kernel symbol found @ 0xFFFFFFC000081000
CSREG: Board 'ARM Juno development board' not known
I've raised this as an issue internally and will get back to you when I know more.
Cheers,
Ash.
The Device Tree has changed for Juno since r0 and r1 came out -- CSAL seems to simply strcmp against the /proc/cpuinfo Hardware line, and looks for "ARM Juno development board"
Unfortunately since a little while back, Juno r0 /proc/cpuinfo (from the device tree) is "ARM Juno development board (r0)" and r1 is "ARM Juno development board (r1)" which isn't the same string..
ARM Juno development board (r0)
ARM Juno development board (r1)
I think newer CSAL (from DS-5 5.22) works here.. it puts a null character behind the bracket to work around this stuff. I don't know if that would have been present in DS-5 5.21, and in DS-5 5.20 the registration system was different..
Thanks for the responses!
I also run into issues when strncmp the Hardware line /proc/cpuinfo but it is because my /proc/cpuinfo does not have a Hardware line.
Dumping my /proc/cpuinfo I see:
root@genericarmv8:~# cat /proc/cpuinfo processor : 0 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd07 CPU revision : 1 processor : 1 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd07 CPU revision : 1 processor : 2 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 3 processor : 3 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 3 processor : 4 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 3 processor : 5 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 3 root@genericarmv8:~#
root@genericarmv8:~# cat /proc/cpuinfo
processor : 0
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x1
CPU part : 0xd07
CPU revision : 1
processor : 1
processor : 2
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 3
processor : 3
processor : 4
processor : 5
root@genericarmv8:~#
Digging a little into this my kernel/module info:
root@genericarmv8:~# uname -a Linux genericarmv8 4.2.0-rc3 #1 SMP PREEMPT Wed Aug 26 11:24:42 UTC 2015 aarch64 GNU/Linux root@genericarmv8:~# lsmod Module Size Used by root@genericarmv8:~# ls /lib/modules/ 3.10.0-1-linaro-lt-vexpress64 3.18 root@genericarmv8:~#
root@genericarmv8:~# uname -a
Linux genericarmv8 4.2.0-rc3 #1 SMP PREEMPT Wed Aug 26 11:24:42 UTC 2015 aarch64 GNU/Linux
root@genericarmv8:~# lsmod
Module Size Used by
root@genericarmv8:~# ls /lib/modules/
3.10.0-1-linaro-lt-vexpress64 3.18
Like my previous post stated I am using the latest prebuilt binaries: juno-latest-oe-uefi.zip and the prebuilt LAMP image: lt-vexpress64-openembedded_lamp-armv8-gcc-4.9_20150620-722.img.gz.
I would expect to have the 4.2 modules in the /lib/modules folder. How did you build/setup your board?
Hello,
You don't need any modules when using the prebuilt binaries, everything you need is built into the kernel rather than built as separate modules.
The issue is that the check for known boards is looking for "Juno", but finds "ARM Juno development board". Note that the "(r0)" and "(r1)" are actually stripped away before the comparison, so that wasn't the problem.
To fix this, edit the following file: /DS-5Examples/CoreSight_access/demos/cs_demo_known_boards.c, changing line 470 to be this:
.hardware = "ARM Juno development board",
Then recompile the example:
/DS-5Examples/CoreSight_access/demos # make clean /DS-5Examples/CoreSight_access/demos # make tracedemo DEBUG=1 LPAE=1 VA64=1
/DS-5Examples/CoreSight_access/demos # make clean
/DS-5Examples/CoreSight_access/demos # make tracedemo DEBUG=1 LPAE=1 VA64=1
You'll also want to recompile the library with the LPAE and VA64 flags if you hadn't before:
/DS-5Examples/CoreSight_access/build # make clean /DS-5Examples/CoreSight_access/build # make DEBUG=1 LPAE=1 VA64=1
/DS-5Examples/CoreSight_access/build # make clean
/DS-5Examples/CoreSight_access/build # make DEBUG=1 LPAE=1 VA64=1
Make sure you've disabled CPUIdle:
# for i in 0 1 2 3 4 5; > for j in 0 1 2; > echo 1 > /sys/devices/system/cpu/cpu$i/cpuidle/state$j/disable; > done; > done;
# for i in 0 1 2 3 4 5;
> for j in 0 1 2;
> echo 1 > /sys/devices/system/cpu/cpu$i/cpuidle/state$j/disable;
> done;
Make sure you've powered on the Juno's debug logic by running the CSAT script provided in the /DS-5Examples/CoreSight_access/demos/juno_demo_setup folder from your host PC connected to a DSTREAM.
Now you can run the demo:
/DS-5Examples/CoreSight_access/bin/dbg # ./tracedemo
And this should now work:
./tracedemo Default configuration, no CPU affinity selected. ITM disabled. kernel symbol found @ 0xFFFFFFC000081000 CoreSight demonstrator ** Currently affine CPUs: #0 #1 #2 #3 #4 #5 CSREG: Detected 'ARM Juno development board' board CSDEMO: Registering CoreSight devices... 0020010000: 2.3 961 00000480 00/0F type= 6 - SINK BUFFER(64K) LINK [TMC - ETF mode] 0020020000: 4.1 906 00040800 00/0F type=10 - CTI 0020030000: 1.1 912 000000A0 00/0F type= 8 - SINK PORT [TPIU] 0020040000: 2.1 908 00000034 00/0F type= 4 - LINK [FUNNEL: 8 in ports] 0020070000: 1.2 961 00002340 00/0F type= 7 - SINK BUFFER(ETR r/w size: 4K) [TMC - ETR mode] 0020100000: 3.6 963 00010000 00/0F type= 3 - SOURCE SWSTIM(65536) [STM ext ports only, 128 masters] 0020110000: 4.1 906 00040800 00/0F type=10 - CTI 0020120000: 2.2 909 00000002 00/0F type= 5 - LINK [REPLICATOR: 2 out ports] 0020130000: 2.1 908 00000033 00/0F type= 4 - LINK [FUNNEL: 8 in ports] 0020140000: 2.3 961 00000480 00/0F type= 6 - SINK BUFFER(64K) LINK [TMC - ETF mode] 0020150000: 2.1 908 00000032 00/0F type= 4 - LINK [FUNNEL: 8 in ports] // ... // ... // ...
./tracedemo
CSREG: Detected 'ARM Juno development board' board
CSDEMO: Registering CoreSight devices...
0020010000: 2.3 961 00000480 00/0F type= 6 - SINK BUFFER(64K) LINK [TMC - ETF mode]
0020020000: 4.1 906 00040800 00/0F type=10 - CTI
0020030000: 1.1 912 000000A0 00/0F type= 8 - SINK PORT [TPIU]
0020040000: 2.1 908 00000034 00/0F type= 4 - LINK [FUNNEL: 8 in ports]
0020070000: 1.2 961 00002340 00/0F type= 7 - SINK BUFFER(ETR r/w size: 4K) [TMC - ETR mode]
0020100000: 3.6 963 00010000 00/0F type= 3 - SOURCE SWSTIM(65536) [STM ext ports only, 128 masters]
0020110000: 4.1 906 00040800 00/0F type=10 - CTI
0020120000: 2.2 909 00000002 00/0F type= 5 - LINK [REPLICATOR: 2 out ports]
0020130000: 2.1 908 00000033 00/0F type= 4 - LINK [FUNNEL: 8 in ports]
0020140000: 2.3 961 00000480 00/0F type= 6 - SINK BUFFER(64K) LINK [TMC - ETF mode]
0020150000: 2.1 908 00000032 00/0F type= 4 - LINK [FUNNEL: 8 in ports]
// ...
I hope that helps.
Thanks again for bring this issue to our attention
Thanks for looking into this Ash!
Even after patching the source, ensuring cpuidle is disabled, and rerunning the CSAT script I still am seeing the following output:
root@genericarmv8:~/CoreSight_access/bin/dbg# ./tracedemo Default configuration, no CPU affinity selected. ITM disabled. kernel symbol found @ 0xFFFFFFC000082000 CoreSight demonstrator ** Currently affine CPUs: #0 #1 #2 #3 #4 #5 CSREG: Failed to detect the board!
root@genericarmv8:~/CoreSight_access/bin/dbg# ./tracedemo
I am using the latest prebuilt binaries: juno-latest-oe-uefi.zip and the prebuilt LAMP image: lt-vexpress64-openembedded_lamp-armv8-gcc-4.9_20150620-722.img.gz. found in the getting started guide: Linaro Releases
I believe it because my /proc/cpuinfo has no "Hardware" line:
root@genericarmv8:~/CoreSight_access/bin/dbg# cat /proc/cpuinfo
What does your /proc/cpuinfo look like? What binary/images are you using?
Ah, I believe this is due to this patch to the Linux kernel which has made it into the Latest kernel (which is the one you're using, in 'juno-latest-oe-uefi.zip'), whereas it's not yet made it into the LSK as this is the Linaro Stable Kernel. I was building from source and using the LSK which is why it worked for me.
I've informed the maintainers of the CoreSight demo to let them know, but in the mean time I suggest you follow the instructions at the Linaro ARM Platforms Page in order to build your software stack with the LSK rather than the Latest kernel.
As a side note, if you want to disable the CONFIG_STRICT_DEVMEM flag for your kernel, the simplest way to do it is after running this command (when following the steps on the Platforms page):
repo sync -j8
After running that command and before continuing, open the file /linux/linaro/configs/distribution.conf and change this line:
Changing the "y" to "n". You can then continue to follow the instructions as normal.
Success!!!
Building with the LSK instead of the latest successfully fixed the /proc/cpuinfo out which allowed the CoreSight tracedemo to run.
Thank you so much for the help Ash! You've been a great resource!
No problem, glad to hear it's working for you now
Hello I have a similar problem, but I am working with a xilinx zybo board, after I execute the tracedemo program i get:
$ ./tracedemo
kernel symbo
And then the system hangs. Any suggestion?
From <DS-5>/examples/CoreSight_Access_Library.zip/DS-5Examples/CoreSight_access/demos/cs_demo_known_boards.c:
const struct board known_boards[] = { { .do_registration = do_registration_arndale, .n_cpu = 2, .hardware = "ARNDALE", }, { .do_registration = do_registration_tc2, .n_cpu = 5, .hardware = "ARM-Versatile Express", }, { .do_registration = do_registration_juno, .n_cpu = 6, .hardware = "Juno", }, { .do_registration = do_registration_altera, .n_cpu = 2, .hardware = "Altera SOCFPGA", }, { .do_registration = do_registration_snowball, .n_cpu = 2, .hardware = "ST-Ericsson Snowball platform", }, { .do_registration = do_registration_axx5500, .n_cpu = 16, .hardware = "LSI Axxia", }, {} };
The Xilinx Zybo board is not listed as a known board and therefore is not supported.
Hello Ash,
Thank you for your reply. Yes i notice that is not supported, however the documentation found here:
https://developer.arm.com/products/software-development-tools/ds-5-development-studio/resources/tutorials/on-target-trac…
Says:
csregistration.c
My question is how can I add that registration function and what parameters do I need to do it. I imagine that i could modify for example the registration file for the snowball platform which features two cortex-a9 cores as the zybo board. Is it possible or just there is not enough information for me do add the function to get coresight to work for my board?
static int do_registration_snowball(struct cs_devices_t *devices)
{
enum { A9_0, A9_1 };
......
Best Regards,
Raul.
I managed to get an Altera DE1-SoC board. I have successfully booted linux using the precompiled images provided by altera. Now I want to perform some instruction tracing of an application. I have been following the tutorial provided here:
DS-5 Development Studio | On-Target Trace Using the CoreSight Access Library – ARM Developer
I managed to compile the tracedemo program and I executed it to generate the trace files (attached). However I still do not fully understand how this program works:
Let's say that I have a myapp.c file. Typically i would compile and execute this program. But how can I generate a instruction trace of this program?
Should I modify the tracedemo.c file to include the code of myapp program? If so where should I add this source code? Is there an example that I can use?