Hi,
I am developing a simple low level motor control application using Arm Cortex A9 core with HPS fabric of Cyclone V SoC FPGA.I am using Arm Development Studio v2024.0-1 tool set to build the code.
Does Cortex A9 cache controller supports to load and execute a critical piece of code from one of the 4 WAY of internal 32kB Instruction cache to achieve deterministic code performance ?Unfortunately running the code from on-chip ram violates our timing requirements due to latency caused by system bus matrix and slow memory access.I am aware that Cortex Mx core cache controller supports loading/executing the critical code in one of the cache WAY and locking it so that it always get cache hit condition.I couldn't find similar feature described in Arm Cortex A9 technical reference manual.
Best Regards,Naresh