Arm Development Platforms forum CCN-508 as OCM(on-chip-memory)

CCN-508 as OCM(on-chip-memory)

Mitsuki Hino 7 days ago

Hi ARM experts,

We need to know in LX2160A cortex A72 from NXP how to put the CCM-508 as OCM, below are the thing we found until now but we need help in how to implemented in c code

Details

1 Configure CCN-508 registers in Trusted Firmware-A (ATF)

ARM CoreLink CCN-508 Cache Coherent Network

The CoreLink CCN-508 is a cache coherent interconnect that includes HN-F nodes (for memory) and RN-F/I/S (requesting nodes).

It supports a System Level Cache (SLC), often implemented using the HN-F’s local cache resources.

`POR_HNF_CFG_CTL` (one per HN-F node):

The following bits control OCM behavior:

`hnf_ocm_en` = 1: Enables OCM mode for the HN-F node.

`hnf_ocm_allways_en` = 1: Treat entire node region as OCM

Where to modify the source

NXP fork of Arm ATF

https://github.com/nxp-qoriq/atf/tree/lf_v2.10

See file: soc.c

function: soc_interconnect_config

https://github.com/nxp-qoriq/atf/tree/lf_v2.10/plat/nxp/soc-lx2160a

2 Reserve and Map OCM as Physical Memory

Reserve a contiguous region of physical memory address space corresponding to the size of the OCM (e.g., 2 MB, 4 MB).

Match this region with the total size of enabled SLC/OCM blocks.

Align to the required cache block granularity (e.g., 512KB, 1MB).

3 Set MMU Page Table Attributes

Configure the A72 MMU page tables to map the OCM region using appropriate memory attributes:

Memory type: Normal memory

Inner/Outer Non-Cacheable

Inner Shareable

Read/Write, Execute/Non-execute as needed

4 Declare SRAM Region in Linux Device Tree

To prevent the Linux kernel from using the OCM region as general-purpose memory declare the reserved region in the device tree (DTS) and optionally expose as a device (/dev/ocm_sram) or assign to specific kernel modules

Example:

ocm_sram: sram@80000000 {

compatible = "mmio-sram";

reg = <0x0 0x80000000 0x0 0x200000>; // base addr + size

no-map;

};

May you please help with some c code examples?

Thanks ind advance.