• State Suggested Answer
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 22 subscribers
  • Views 252 views
  • Users 0 members are here
Options
Related
How was your experience today?

related to AXI4

mayank123

HI,

if I am write something like that

initial begin
$dumpfile("dump.vcd");
$dumpvars(1);

#100ns rst_n = 0;
#100ns rst_n = 1;

// Align to negedge to drive traffic
#5ns;

awaddr = 'h15;
awvalid = 1;

#10ns
awaddr = 'h25;
wvalid = 1;
wdata = 'h10;

#10ns
awaddr = 'h35;
wdata = 'h20;

#10ns
awvalid = 0;
wdata = 'h30;

#10ns
wvalid = 0;

#100ns
$finish();

What should be come out for first Address 0x15 or 0x25 for slave according to axi4 protocol.

BR,

Mayank 

Parents
  • 0

    There's a lot of information missing from the above description, but I'll assume that AWREADY and WREADY were both high throughout, that AWLEN=0 (single transfers) and WLAST was high for each WVALID high cycle.

    Note also that AXI only uses rising edges of the clock for events, so you shouldn't align traffic to the falling edge of the clock as this reduces setup times. Perhaps a delay of #1ns to indicate a propagation delay from ACLK rising edges, but not a half clock cycle delay.

    From what I understand from the above sequence it looks like you have indicated 3 transactions...

    1st is AWADDR=0x15 with WDATA=0x10 following a cycle later

    2nd is AWADDR=0x25 with WDATA=0x20 a cycle later

    3rd is AWADDR=0x35 with WDATA=0x30 a cycle later

    The obvious ordering then is that address 0x15 comes out first, then 0x25, then 0x35, as that is the time ordering your stimulus suggests, so I'm wondering what you are concerned about ?

Reply
  • 0

    There's a lot of information missing from the above description, but I'll assume that AWREADY and WREADY were both high throughout, that AWLEN=0 (single transfers) and WLAST was high for each WVALID high cycle.

    Note also that AXI only uses rising edges of the clock for events, so you shouldn't align traffic to the falling edge of the clock as this reduces setup times. Perhaps a delay of #1ns to indicate a propagation delay from ACLK rising edges, but not a half clock cycle delay.

    From what I understand from the above sequence it looks like you have indicated 3 transactions...

    1st is AWADDR=0x15 with WDATA=0x10 following a cycle later

    2nd is AWADDR=0x25 with WDATA=0x20 a cycle later

    3rd is AWADDR=0x35 with WDATA=0x30 a cycle later

    The obvious ordering then is that address 0x15 comes out first, then 0x25, then 0x35, as that is the time ordering your stimulus suggests, so I'm wondering what you are concerned about ?

Children
No data