Hi,
I am using arm fast model tools to build a simple system consisting of R82x1 single core cluster, a RAM, UART and GIC IRI. I can run a simple demo that read/writes to UART and I can see UART prints successfully. What doesn't work is GIC IRI. Somehow the R82 core is unable to read/write to GICIRI over its pvbus and I get bus faults. I can write to UART addresses but not this one. MPU is configured to allow the accesses, but it still does not work. I connect the UART, SRAM, and GIC IRI controller through a decoder with following address map. Any ideas what I maybe missing? pvbusdecoder.pvbus_m_range[0x0..0x7fffff] => ramdevice.pvbus; pvbusdecoder.pvbus_m_range[0x100000000..0x10000ffff] => pl011_uart.pvbus;pvbusdecoder.pvbus_m_range[0x110000000..0x1101fffff] => gic_iri.pvbus_s;Here is full Lisa code:
component r82simple{
composition { base_powercontroller : Base_PowerController("CPU-available-mask"=0x1); gic_iri : GIC_IRI("print-memory-map"=1,"CPU-affinities"="0.0.0.0","reg-base"=0x110000000,"reg-base-per-redistributor"="0.0.0.0=0x110100000","has-two-security-states"=1,"ITS0-base"=0x110020000,"GITS_BASER0-type"=1,"GITS_BASER2-type"=2,"GITS_BASER6-type"=4,"processor-numbers"="0.0.0.0=0","supports-shareability"=1,"A3-affinity-supported"=0,"ITS-TRANSLATE64R"=1,"ARE-fixed-to-one"=0,"wakeup-on-reset"=0,"GICD_CTLR-DS-1-means-secure-only"=1); ambapv2pvbus : AMBAPV2PVBus(); memorymappedcountermodule : MemoryMappedCounterModule("non_arch_start_at_default"=1,"use_real_time"=1); telnetterminal : TelnetTerminal(); clockdivider : ClockDivider("mul"=24000000); pl011_uart : PL011_Uart("uart_enable"=0,"untimed_fifos"=1,"out_file"="","unbuffered_output"=0,"enable_dc4"=0); ramdevice : RAMDevice("size"=0x800000); pvbusdecoder : PVBusDecoder(); Core : ARMCortexR82x1CT("BROADCASTCACHEMAINT"=0,"BROADCASTOUTER"=0,"PA_SIZE"=48,"core_power_on_by_default"=1,"enable_simulation_performance_optimizations"=1,"has_llpp"=0,"has_spp"=0,"memory.has_llram"=0,"memory.llram_base"=0x30000000,"memory.llram_enable_at_reset"=0); Clock100MHz : ClockDivider(mul=100000000); Clock1Hz : MasterClock() }
connection { Clock1Hz.clk_out => Clock100MHz.clk_in; Clock100MHz.clk_out => Core.clk_in; clockdivider.clk_out => pl011_uart.clk_in_ref; pl011_uart.serial_out => telnetterminal.serial; Clock1Hz.clk_out => clockdivider.clk_in; Clock100MHz.clk_out => memorymappedcountermodule.clk_in; memorymappedcountermodule.cntvalueb => Core.cntvalueb; Core.pvbus_m0 => pvbusdecoder.pvbus_s; self.amba_pv_s_utility_bus => ambapv2pvbus.amba_pv_s; ambapv2pvbus.pvbus_m => Core.utility_bus_s; pl011_uart.intr => gic_iri.spi_in[0]; gic_iri.pvbus_m => pvbusdecoder.pvbus_s; pvbusdecoder.pvbus_m_range[0x0..0x7fffff] => ramdevice.pvbus; pvbusdecoder.pvbus_m_range[0x100000000..0x10000ffff] => pl011_uart.pvbus; base_powercontroller.cpuporeset[0] => Core.reset; base_powercontroller.l2reset[0] => Core.presetdbg[0]; base_powercontroller.l2reset[0] => Core.l2reset; base_powercontroller.system_reset => gic_iri.po_reset; base_powercontroller.system_reset => gic_iri.reset; gic_iri.wake_request[0] => base_powercontroller.wakerequest[0]; Core.dbgnopwrdwn[0] => base_powercontroller.dbgnopwrdwn[0]; Core.standbywfi[0] => base_powercontroller.standbywfi[0]; pvbusdecoder.pvbus_m_range[0x110000000..0x1101fffff] => gic_iri.pvbus_s; gic_iri.redistributor_m[0] => Core.gicv3_redistributor_s[0]; } behavior init() { composition.init(); }
behavior reset(int level) { composition.reset(level); }
properties { component_type = "System"; } slave port<AMBAPV> amba_pv_s_utility_bus;}