I am using GIC 600. I am doing one experiment.
Problem statement: When the core runs a critical section by disabling interrupt (ie I and F bit from CPSR), and is stuck somewhere, then HW trigger as interrupt disable
Want to make WDT as NMI by setting GICC_PMR register.
Configured all interrupt priority as 0x20 and WDT has priority 2. GICC PMR register set as 1
Instead of disabling the I and F bit from CPSR, set the PMR register.
For mask interrupt: GICC_PMR = 0x1
For unmasking interrupt: GICC_PMR = 0xF8
While running the critical section(PMR value was 1), SGI came and was in a pending state. When it exits from the critical section, the written value (GICC_PMR = 0xF8) is successful but the IRQ handler is not called for that pending SGI
Sample code for writing PMR value
__asm volatile("DSB ISHST"); __asm volatile ( "MCR p15, 0, %0, c4, c6, 0" :: "r"(PMRValue) ); __asm volatile ( "DSB SY" );