GICD_IGRPMODR[0] register read as 0

Namu said:

1) Can you please tell me why this register behaves differently?

There's a few reasons why GICD_IGRPMODn might read as 0 when it in reality it has a different value. 

• If DS is 0, then GICD_IGRPMODn is RAZ/WI (read as zero, ignore writes) to all Non-secure accesses.  Note, it's the security of the access that matters, not which state the access came from.  When in Non-secure state, all accesses are Non-secure.  When in Secure state, you can generate both Secure AND Non-secure accesses (controlled by the NS bits in the translation tables)
• If DS is 1, or the ARE bits are 0, the register is RES0.

Namu said:

   B) When affinity routing is enabled for the Secure state, GICD_IGRPMODR0 is RES0 and equivalent functionality is proved by GICR_IGRPMODR0.

It could perhaps be explained better, but it's not a contradiction.  

The ARE bits control whether the GIC is in legacy/GICv2 mode (ARE=0 means legacy).  

When ARE_S=0, ALL the GICD_IGRPMODR<n> registers are RES0, because these registers didn't exist in GICv2.

When ARE_S=1, specifically GICD_IGRPMODR0 is RES0.  This is because GICD_IGRPMODR0 covers INTIDs 0..31, and in GICv3 those INTIDs are controlled via the per-PE GICR registers. 

Namu said:

3) What is the value of RES0? Is there any difference between RES and RES0?

RES0 means "Reserved, Should be Zero or Preserved".  For the full definition of RES0 see the Glossary in the Arm Architecture Reference Manual.

Thanks, Mr. Martin for the details.

I checked the address of the register in the code. The offset of the register is 0x0D04 meanings its GICD_IGRPMODR[1] register. 

While accessing GICD_IGRPMODR[1], Our system is in a secure state, and the DS = 0, ARE_s = 1, ARE_NS=1(ie  GICD_CTLR = 0x30)

1) Does Any other configuration affect the GICD_IGRPMODR[1] to become RES0?

2) Any idea, How to check what is access mode( Non-secure accesses, and secure access) while accessing the register

Thank you in advance