MMU Level 3 table configuration on a53 core

Hello Experts,

I have a problem with establishing the level 3 table in MMU for cortex-a53 processor. Level 1 and Level2 table works as expected but I need a 4KB memory block for my project. Below is the code that I wrote to configure the mmu. Could someone look at what is wrongly set so that the level 3 table is not configured correctly?  

MOV x0, #0x44 /* Inner/outer cacheable WB */
MSR mair_el3, x0
/* Invalidate TLBs at the current exception level */
TLBI alle3

/* RES1
RES1
PS 40-bit
ORGN0 outer WB no WA cacheable
IRGN0 inner WB no WA cacheable
T0SZ 39-bit region size */
LDR x0, =(1 << 31) | (1 << 23) | (2 << 16) | (3 << 10) | (3 << | 25
MSR tcr_el3, x0

/* Page table setup */

LDR x1, =ttb // Address of L1 table

//0x0000,0000 - 0x3FFF,FFFF
LDR x2, =ttb1 // Get address of L2 table
MOV x0, #0x03 // Entry template for pointer to next level table
ORR x0, x0, x2 // Combine template with L2 table Base address
STR x0, [x1]

//0x4000,0000 - 0x7FFF,FFFF
MOV x0, #0x405 // Entry template

ORR x0, x0, #0x40000000 // 'OR' template with base physical address
STR x0, [x1, #8]

LDR x1, =ttb1 // Address of L2 table

//0x0000,0000 - 0x2000,0000
MOV x0, #0x401
MOV x2, #0x100
1:
STR x0, [x1], #8
ADD x0, x0, #0x200000 // Increment the physical address field
SUB x2, x2, #1
CBNZ x2, 1b

//0x2000,0000 - 0x3400,0000 (Fault)
MOV x0, #0x0
ORR x0, x0, #0x20000000 // 'OR' template with base physical address
MOV x2, #0xA0
1:
STR x0, [x1], #8
ADD x0, x0, #0x200000 // Increment the physical address field
SUB x2, x2, #1
CBNZ x2, 1b

//0x3400,0000 - 0x3480,0000 (SDRAM)

mov x0, #0x401
MOV x6, #0x34000000
ORR x0, x0, x6 // 'OR' template with base physical address
MOV x2, #2
1:
STR x0, [x1], #8
ADD x0, x0, #0x200000 // Increment the physical address field
SUB x2, x2, #1
CBNZ x2, 1b

LDR x2, =ttb2 // Get address of L3 table
MOV x0, #0x03 // Entry template for pointer to next level table
ORR x0, x0, x2 // Combine template with L3 table
STR x0, [x1]

MOV x0, #0x405 // Entry template

MOV x6, #0x34600000
ORR x0, x0, x6 // 'OR' template with base physical address
STR x0, [x1, #8]

LDR x1, =ttb2 // Address of L3 table

//0x3440,0000 - 0x3460,0000
MOV x0, #0x401
MOV x6, #0x34400000
ORR x0, x0, x6 // 'OR' template with base physical address
MOV x2, #0x200
1:
STR x0, [x1], #8
ADD x0, x0, #0x1000 // Increment the physical address field
SUB x2, x2, #1
CBNZ x2, 1b
DSB SY

/* Ensure all translation table writes have drained into memory,
the TLB invalidation is complete,
and translation register writes are committed before enabling the MMU */
DSB ISH
ISB
LDR x0, =ttb // Address of L1 table
MSR ttbr0_el3, x0 // set TTBR

MRS x0, S3_1_c15_c2_1 // cpuectlr_el1
ORR x0, x0, #0x40
MSR S3_1_c15_c2_1, x0

MRS x0, sctlr_el3
bic x0, x0, #(1 << 1) /* clear A, disable alignment fault check */
/* I enable instruction cache
C enable data and unified caches
M enable EL3 MMU */
LDR x1, =(1 << 12) | (1 << 2) | 1
ORR x0, x0, x1 /* set bits */
MSR sctlr_el3, x0
/* Ensure the MMU enable takes effect immediately */
ISB