I'm trying to find the 'AHB lite to AHB wrapper' on ARM Developer Download, but I can't seem to locate it. Do you know where I can obtain it?
Most AHB based designs nowadays use AHB-lite or AHB5 as the bus protocol.
The original AHB (actually AHB2) supported multiple bus masters all sharing a single bus. Each master would use an HBUSREQ/HGRANT arbitration handshake to request control of the shared bus. As only one master could be active at any one time this led to comparatively poor system performance.
So designs then started moving to multi-layer structures, with only one master on each layer, and using a BusMatrix interconnect component to support multiple masters accessing shared targets. With each master on its own layer you could have parallel accesses, so much better for system performance.
The bus protocol didn't then need the HBUSREQ/HGRANT support, so AHB2 was simplified to become AHB-lite, and the later AHB5 was then an evolution of the simple AHB-lite protocol, adding a few features to the simpler AHB-lite features.
So when you are looking for an AHB-lite to AHB wrapper, is this to add the HBUSREQ and HGRANT arbitration signals ?
Unfortunately we don't now have any AHB2 support on our development system components, so wouldn't have a wrapper going from a higher performing AHB-lite protocol to the lower performing AHB2. Instead I would recommend trying to look at an AHB-lite multi-layer type approach for your design so that you are not then restricted by only having one master active at a time.
You can connect an AHB2 bus master to an AHB-lite system simply by tying the HGRANT input high and ignore the HBUSREQ. HLOCK would also need retiming to become the AHB-lite HMASTLOCK control. This would be done by registering HLOCK on HCLK rising edges when HREADY is high, so performing the same retiming the AHB2 bus arbiter would do when generating HMASTLOCK.
But there is no simple connection to connect an AHB-lite master to an AHB2 based system as adding the HBUSREQ and HGRANT logic would require state machines to recognise when the master needs to be stalled, and also to then handle the AHB2 system responses of SPLIT or RETRY.