How to understand Device-nGRE?

Hi Ash,

in the case of Device-nGnRE, what does IMPLEMENTATION DEFINED block size means?

Is it related to (according to the Armv8 architecture specification)

A Memory-mapped peripheral occupies a memory region of IMPLEMENTATION DEFINED size and
can be accessed using load and store instructions.

My misunderstanding comes from the Armv7a specification which states:

in A3.8.2 Ordering requirements for memory accesses:

The size of a memory mapped peripheral, or a block of memory, is IMPLEMENTATION DEFINED, but is not smaller
than 1KByte.

Note: This implies that the maximum memory-mapped peripheral size for which the architecture guarantees order for all
implementations is 1KB.

If the pheriperal has a memory map greater than 1KB, the Armv7 architecture doesn't guarantee ordering? If true, does the same limitation

exist for Armv8, for the Device-nGnRE? 

Bas

Hi Ash,

in the case of Device-nGnRE, what does IMPLEMENTATION DEFINED block size means?

Is it related to (according to the Armv8 architecture specification)

A Memory-mapped peripheral occupies a memory region of IMPLEMENTATION DEFINED size and
can be accessed using load and store instructions.

My misunderstanding comes from the Armv7a specification which states:

in A3.8.2 Ordering requirements for memory accesses:

The size of a memory mapped peripheral, or a block of memory, is IMPLEMENTATION DEFINED, but is not smaller
than 1KByte.

Note: This implies that the maximum memory-mapped peripheral size for which the architecture guarantees order for all
implementations is 1KB.

If the pheriperal has a memory map greater than 1KB, the Armv7 architecture doesn't guarantee ordering? If true, does the same limitation

exist for Armv8, for the Device-nGnRE? 

Bas