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How do the TLB maintenance instructions affect other offline CPU cores disabled by CPU Hotplug in the kernel


I'm a beginner in ARM architecture. 

1) Are some TLBI instructions that can clean TLB entry for the Outer Shareable domain valid for other CPU cores that are offline? For example, if I make a CPU core to power down by CPU Hotplug in the Linux, can such TLBI instruction still clean up the TLB entries from this offline core, and how does it be effective?

2) And I wonder if there are any situations that might fail the TLB invalidation.


  • Why do you need to clean the TLB entries for a core that is powered down and offline? If it's powered off, then it _can't_ do anything. It has no power.

    The core will need invalidate its TLBs when getting powered on again, as part of the power up sequence.