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AXI Unaligned Transfers Address Clarification

Hi, we are implementing AXI-Lite interface with 64 bits data transfer bus on WDATA with 8 bits WSTRB implemented. Assuming that we have a data transfer of address 0x04, which is non address align to the data with, base on unaligned transfer, master permit to either use lower-order unaligned start address or align start address with strobe signals to indicate unaligned transfer (as below 2 bullet). Please help to verify below interpretation is correct.

Bullet 1 : We can actually use address 0x04 which is unaligned to 64 bits data width transfer, to indicate the starting data is unaligned to data bus.

OR optionally we can also use Bullet 2 : use address 0x00 instead, which is aligned address, with writestrobe of 0xF0 to indicate upper 4 bytes are valid.

Is this above 2 interpretation accurate?


If above interpretations is accurate, What is the interpretations at the Note "The information's on the low-order address lines must be consistent with the information's on the byte lane strobes"? Is the consistent here referring to the lower address must indicate where the 1st LSB bits of the strobe locations? 

Or consistent here means that the number of strobe assertion cannot be larger then bytes transfer indicate in lower address (example of violations : address 0x04 with write strobe 0xFF indicate of inconsistancy)