Debug Issue on embedded Cortex-M3 of SmartFusion2 : No source available for "0x0"

Hello, 

I am currently developing an FPGA architecture on Smartfusion2, where the cortex-m3 should control and update the different FPGA cores' registers. I exported the firmware using Libero SoC and created a "C" application using SofConsole 4. The issue is when I debug the program it shows this error: No source available for "0x0" 

The full log is listed below: 

Open On-Chip Debugger 0.8.0 (2015-10-14-11:51)

Licensed under GNU GPL v2
For bug reports, read
openocd.sourceforge.net/.../bugs.html
M2S150
Info : only one transport option; autoselect 'jtag'
adapter speed: 2000 kHz
cortex_m reset_config sysresetreq
trst_only separate trst_push_pull
do_board_reset_init
Started by GNU ARM Eclipse
Info : FlashPro ports available: E2001O6WGW
Info : FlashPro port used: E2001O6WGW
Info : clock speed 2000 kHz
Info : JTAG tap: M2S150.tap tap/device found: 0x1f8061cf (mfg: 0x0e7, part: 0xf806, ver: 0x1)
Info : JTAG tap: M2S150.tap disabled
Info : JTAG tap: M2S150.dap enabled
Info : M2S150.cpu: hardware has 6 breakpoints, 4 watchpoints
Info : accepting 'gdb' connection from 3333
undefined debug reason 7 - target needs reset
Info : JTAG tap: M2S150.tap tap/device found: 0x1f8061cf (mfg: 0x0e7, part: 0xf806, ver: 0x1)
Info : JTAG tap: M2S150.tap disabled
Info : JTAG tap: M2S150.dap enabled
target state: halted
target halted due to debug-request, current mode: Thread
xPSR: 0x01000000 pc: 0x0000da34 msp: 0x20003308
lr (/32): 0x00000000
semihosting is enabled
===== arm v7m registers
(0) r0 (/32): 0x40020A1C
(1) r1 (/32): 0x20003D7A
(2) r2 (/32): 0x00000000
(3) r3 (/32): 0x40020800
(4) r4 (/32): 0x7560B55A
(5) r5 (/32): 0x7C7713B7
(6) r6 (/32): 0x66BD96FB
(7) r7 (/32): 0x2000FFD8
(8) r8 (/32): 0x4ADDDF59
(9) r9 (/32): 0xE7BE1FF0
(10) r10 (/32): 0xC5BB6FEF
(11) r11 (/32): 0x00000000
(12) r12 (/32): 0xE2AFEA71
(13) sp (/32): 0x20010000 (dirty)
(14) lr (/32): 0x00000000 (dirty)
(15) pc (/32): 0x20000190 (dirty)
(16) xPSR (/32): 0x01000000 (dirty)
(17) msp (/32): 0x20003308
(18) psp (/32): 0x9A53960C
(19) primask (/1): 0x00
(20) basepri (/8): 0x00
(21) faultmask (/1): 0x00
(22) control (/2): 0x00
===== Cortex-M DWT registers
(23) dwt_ctrl (/32)
(24) dwt_cyccnt (/32)
(25) dwt_0_comp (/32)
(26) dwt_0_mask (/4)
(27) dwt_0_function (/32)
(28) dwt_1_comp (/32)
(29) dwt_1_mask (/4)
(30) dwt_1_function (/32)
(31) dwt_2_comp (/32)
(32) dwt_2_mask (/4)
(33) dwt_2_function (/32)
(34) dwt_3_comp (/32)
(35) dwt_3_mask (/4)
(36) dwt_3_function (/32)

Does anyone have an idea to solve it? 

thanks