hello, arm expert.
I try to run a zephyr os in aarch64 el2 mode on armv8.1 cpu (cortex-a55). Zephyr can run successful in aarch64 el1 mode on cortex-a55 platform, And as I know, when enable armv8.1 VHE mode, a os can successful run in el2 mode without change the xxx_elx register if it can run successful in el1 mode before. So I do the test, but error occur below:
Through enable VHE mode, Zephyr can run success before enable mmu, but after I write sctlr_el2, things go wrong, and I get a translation fault. The error code seems that it is level3 translation falut, But when I check the far_el2 register , it always keep a fault address where the '_image_ram_end' is(It means that when I try to change the _image_ram_end' address, the value of the fat_el2 keep change with it. I am so confused because when I set addr mapping when build page table , The address of this '_image_ram_end' has no valid address ). It should be noted that '__image_ram_end' is a address where my os kernel segment's end address locate, and in this experience, I use a idmap from virtual address to physical address so I think it not a valid address. Below are some of my register infomation after fault occur:
Before enable mmu, some of register information are below:
I would like to know below question:
It may be caused by date cache, so before i write sctlr_el2 i invalid all the cache, and even disable cache flag in sctlr_el2 register, but it not work.
Hi there, has Alex69 answered your question? If so, please mark it as an accepted answer.
I checked it and find it is because the el2 sp_el2 register have a invalied value. And I must init sp_el2 register before I enable mmu(The Zephyr dose not consider the kernel will run in el2 mode)