I have a proprietary OS Implemented in our Project and its running on ARM Cortex M7. To exit ISR handler we use these 2 instructions.
cpsie i bx LR
The sequence of the flow is as follows
1. Low Priority Task is running. (LowPriority_TASK)
2. Low priority interrupt occurred (LowPriority_ISR). PC jumps to this LowPriority_ISR handler and starts execution.
3. Before exiting this ISR Handler we restore the context of the pre-empted task i.e. LowPriority_TASK. During this Context restoring a new high priority ISR is Triggered. (HighPriority_ISR).
5. Thus immediately after cpsie i, the PC jumps to HighPriority_ISR handler. In this HighPriority_ISR handler we have set few Events which makes a Higher priority Task (HighPriority_TASK) in ready state.
6. HighPriority_ISR is finished and the PC returns to LowPriority_ISR. Here there only one instruction bx LR pending to be executed. PC executes this instruction and the control is passed to LowPriority_TASK. Even though the HighPriority_ISR is in ready state the scheduler cannot load it till next task or ISR is triggered.
Although this problem will not occur if there is single atomix instruction available which will load the context and enable interrupts e.g rfe sp! or ret which is not available in Cortex M7
DO any body have faced this type of issue. if yes is there any solution for this.
Hello, if I am reading this correctly, I do not believe the (re)enable interrupts ('cpsie i') instruction is necessary. The exception return instruction ('bx lr' in your example) should restore everything as necessary.
Thank you for the Reply. And apologies to comment late. I tried using the only Bx LR instruction instead of Cpsie i and bx LR. But i am still facing the issue. I am investigating it further from OS code point of view.