Dear all,
Can anyone help me in better understanding/correcting the below
Memory mapped IO means that an address range is directly mapped to physical addresses (devices). Any access to MMIO region bypass the MMU (and perhaps bypass cache as well.). As an ARM example the GIC is a typical MMIO?
- When a Linux process want to access to access an ARM MMIO say at 0xAAAAFFFF, how is this access accomplished,? how does the system/runtime knows that this is is an actual physical address to bypass the MMU. Or otherwise the this MMIO must be first mapped into the accessing process virtual address space and subjected to typical VA-PA translation mechanism ...
-In case the platform has a master bus peripheral which can generate addresses on the bus for read write and having the same view of memory and shared hardware. Are the agent addresses independent 'virtual addresses' that must be mapped to physical ones througth the SMMU and the IO page table. Can anyone explain to me what happen exactly?
Thank you so much
I may be misunderstanding you, but software can't bypass the MMU. While the MMU is enabled, all addresses used by the core be subject to the MMU.
Did you mean "flat mapped" (i.e. VA==PA)? If so, this isn't bypassing the MMU. Rather it's just that software has set the VA to be the same as PA in the translation tables. The MMU still goes through the same translation steps, and the access would still be subject to MMU checks (such as access permission checking).
I'm not a Linux expert, but I can't immediately see why you'd particularly want to flat map the GIC.
A SMMU can be used to give a master (e.g. a DMA controller) the same view of memory as software running on the processor. Take a DMA transfer as an example...
You have two large buffers, Src and Dst. You want to use a DMA engine to copy the contents of Src to Dst.
These buffers "look" contiguous in the virtual address space, but are in fact made of multiple small non-contiguous blocks of physical memory.
When setting up the DMA job we could:
* Describe the structure of two buffers in physical memory to the DMA engine. Possibly by turning it into lots of small jobs.
* Use a SMMU to give the DMA engine the same view as software. Meaning it also sees two contiguous regions.