Some questions about the SMMU of JUNO SoC

JUNO SoC provides additional support for virtualization except Cortex-A57/A53 as follows:
The CoreLink GIC-400.
Stage 2 page table translation for masters, that the following provide:
A CoreLink MMU-401 System Memory Management Unit (SMMU) for the following:
- The Embedded Trace Router (ETR).
- PCI Express.
- Each HDLCD controller.
- The DMA-330.
- Thin Links, TLX-400.
A CoreLink MMU-400 SMMU for the Mali-T624 GPU.
Note: The MMU-400 does not support the AArch64 page table format.

1. Since MMU-400 is only compatible with ARMv7 LPAE page table formats, why does it connect with Mali-T624 GPU for virtualization in a ARMv8 SoC?
2. MMU-401 is compatible with ARMv7 and ARMv8, but it only supports Stage 2 address translation. I find that Stage 1 address translation is mainly useful for memory fragmentation management and Stage 2 address translation is intended to benefit Virtual Machine Monitors from System-MMU-Whitepaper-v8.0.pdf. The masters that connect with MMU-401 in JUNO SoC don't have their own MMU, so do the outside SMMUs need also support Stage 1 address translation for memory fragmentation management and virtualization?
Does Stage 2 address translation also support memory fragmentation management?

3.Why not directly use MMU-500 for virtualization in JUNO SoC?