In the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile, there's a description about vttbr_el3: " Register bits[47:x] hold bits[47:x] of the stage 1 translation table base address" . I am a little confused, as far as I know , the vttbr_el3 register hold the stage 3 page table base address, so what's the meaning of " stage 1 translation table base address"?
Also, I tired to open the 3 stage paging in my system liteblue. I setup the 3 stage page table at physical address(0x30000000), and set the vttbr_el3 to this value.However, I got a Data Abort (code: 000101) which means a level 2 translation fault in stage 1 translation. So what's the correct usage of vttbr_el3?
I am using cortex-a53 and here's the related register value I set:
Hello, you seem to be mixing up translation stages with Exception levels. Furthermore, I am not aware of a VTTBR_EL3 register (there is a _EL2 register).
Does the below document help?