Hello,
In the ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile, there's a description about vttbr_el2: " Register bits[47:x] hold bits[47:x] of the stage 1 translation table base address" . I am a little confused, as far as I know , the vttbr_el2 register hold the stage 2 page table base address, so what's the meaning of " stage 1 translation table base address"?
Also, I tired to open the 2 stage paging in my system. I setup the 2 stage page table at physical address(0x20000000), and set the vttbr_el2 to this value.However, I got a Data Abort (code: 000101) which means a level 1 translation fault in stage 2 translation. So what's the correct usage of vttbr_el2?
I am using cortex-a53 and here's the related register value I set:
HCR: 0x80000001
VTCR_EL2: 0x80023558
VTTBR_EL2: 0x20000000
Thanks for your reply.
Actually, I test the address translation in el3 using AT S12E1R,0x10000000 instruction. So I get the result from PAR_EL1 of which the value is "0xa0b"( means the FST code is 0b000101).
In the level 1 page table , I map the 0-1GB space using a block descriptor. The table descriptor at address 0x20000000 is 0x7fd.
The strange thing is, when my system is booting up, I sometimes can get the correct translation while sometimes not. I am wondering wether this is because there are some other system registers which can influence the stage 2 translation which I doesn't set and it reset to a unknown value.
I will appreciate it if you could give me any help.
Are you invalidating the TLBs before enabling second stage translation?
Also, if you contact Arm Support they might have example code that can be shared.
Yes, I invalidated the TLBs by " TLBI ALLE1IS" and "TLBI ALLE2IS". I will try to contact Arm Support for some example code.
And thanks for your help!