I'm reading "ARM® Cortex®-A53 MPCore Processor Technical Reference Manual".
And, in 6.7 Direct access to internal memory part (P.357), there is a problem to understand what is the meaning of AArch64 register 'Operation' part.
I attach a picture of 'Table 6-4 AAarch64 registers used to access internal memory' in 'ARM® Cortex®-A53 MPCore Processor Technical Reference Manual' below.
In the table (Table 6-4 AAarch64 registers used to access internal memory), For example, 'Operation' column of Data Register 0 (1st row) is "MRS <Xd>,
S3_3_c15_c0_0". I'm wondering how to understand the second operand (S3_3_c15_c0_0) of the MRS in the Operation column.
I'm guessing that the operand is separated by under-bars('_') and each of them has its own meaning.
What exactly do these (S3, 3, c15, c0 and 0) represent?
Please give me some advices which how to approach that kind of operations in ARM architecture.
Thanks!
Thank you for your answer. But I could not understand exactly what you mentioned because I'm lack of background about ARM architecture.
As I understand what you mentioned above, the identifiers for system register, such as S3_3_c15_c0_0, should be mapped to the other identifier, such as Data Register 0. Then, is it right that I can use the id (S3_3_c15_c0_0) directly in an assembly code to access the register?
I'm sorry for bother you but, I want to know how I can access directly to the internal memory (cache) by using the feature (6.7 Direct access to internal memory) in 'ARM® Cortex®-A53 MPCore Processor Technical Reference Manual'.
> " Then, is it right that I can use the id (S3_3_c15_c0_0) directly in an assembly code to access the register?"
Yes, you can.