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How to understand AArch64 register 'Operation' column for 'Direct access to internal memory' in Cortex -A53?

nickeys

I'm reading "ARM® Cortex®-A53 MPCore Processor Technical Reference Manual".

And, in 6.7 Direct access to internal memory part (P.357), there is a problem to understand what is the meaning of AArch64 register 'Operation' part.

I attach a picture of 'Table 6-4 AAarch64 registers used to access internal memory' in 'ARM® Cortex®-A53 MPCore Processor Technical Reference Manual' below.

In the table (Table 6-4 AAarch64 registers used to access internal memory), For example, 'Operation' column of Data Register 0 (1st row) is "MRS <Xd>,

S3_3_c15_c0_0". I'm wondering how to understand the second operand (S3_3_c15_c0_0) of the MRS in the Operation column.

I'm guessing that the operand is separated by under-bars('_') and each of them has its own meaning.

What exactly do these (S3, 3, c15, c0 and 0) represent?

Please give me some advices which how to approach that kind of operations in ARM architecture.

Thanks!

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    There are different ways you can think of it...

    At one level, you can think of it as an arbitrary value used to identify a particular register. Where S3_3_c15_c0_0 is simply the identifier chosen for "Data Register 0".

    But taking a step back, the MRS/MSR instructions are how you access system registers.  Within the encodings for these instructions are fields which specify which register it is you want to access.  The architecture defines a long list of registers, then assigns them names and encodings.  For the architected registers (those listed in the Arm ARM), you can write:

      MRS    X0, SCTLR_EL1

    Which the tools (internally) translate to:

      MRS  X0, S3_0_c1_c0_0

    Because SCTLR_EL1 is much easier to remember and write that the underlying encoding information.

    For registers which are specific to a given processor (as is the case here), the tools don't know the names and translations of the registers.  So you have to provide the underlying encoding to the tools.

    Where does the format come from?  If you look back at Armv7-A (and earlier), the architecture talked about coprocessors (CP0 to CP15).  These coprocessors could have registers, which were laid out in a tree-like structure.  In the A32/T32 MCR/MRC instructions, you specified a coprocessor and the register in the hierarchy you wanted to access.  You can find diagrams in the Armv7-A Architecture Reference manual that show these structures.

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  • 0

    There are different ways you can think of it...

    At one level, you can think of it as an arbitrary value used to identify a particular register. Where S3_3_c15_c0_0 is simply the identifier chosen for "Data Register 0".

    But taking a step back, the MRS/MSR instructions are how you access system registers.  Within the encodings for these instructions are fields which specify which register it is you want to access.  The architecture defines a long list of registers, then assigns them names and encodings.  For the architected registers (those listed in the Arm ARM), you can write:

      MRS    X0, SCTLR_EL1

    Which the tools (internally) translate to:

      MRS  X0, S3_0_c1_c0_0

    Because SCTLR_EL1 is much easier to remember and write that the underlying encoding information.

    For registers which are specific to a given processor (as is the case here), the tools don't know the names and translations of the registers.  So you have to provide the underlying encoding to the tools.

    Where does the format come from?  If you look back at Armv7-A (and earlier), the architecture talked about coprocessors (CP0 to CP15).  These coprocessors could have registers, which were laid out in a tree-like structure.  In the A32/T32 MCR/MRC instructions, you specified a coprocessor and the register in the hierarchy you wanted to access.  You can find diagrams in the Armv7-A Architecture Reference manual that show these structures.

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