In the default examples available under ARM Development Studio 2019.1 release version I have picked up startup_Cortex-R8 example.
The default memory configuration details in the scatter file for Cortex-R8 is shown below, but I want to increase the memory size of stack and heap from 16 KB to 1MB.
How can we do this?
Can you please share us more details/steps to make this changes.
Thanks.
There are reserved region names, ARM_LIB_STACKHEAP defines a unified region, with HEAP growing 'up' in memory from the base address, STACK growing 'down' from the upper address. Similarly you could use ARM_LIB_STACK and ARM_LIB_HEAP if you wish to use separate regions.
https://developer.arm.com/documentation/101754/0622/armlink-Reference/Scatter-loading-Features/The-scatter-loading-mechanism/Placing-the-stack-and-heap-with-a-scatter-file
In this example, the base address of the region is 0xC000, and the size is 0x4000 bytes (16KB).
To change the size from the software point of view, simply change 0x4000 > 0x100000, but you must consider the memory map of the target hardware. You will likely also need to change the base address to map to match your hardware. Assuming you are using the supplied FVP, there is RAM available from 0x0 ~ 0x40000000, and so should not be an issue. However, due to the next issue, I recommend locating at a base address of 0x100000:
ARM_LIB_STACKHEAP 0x100000 EMPTY 0x100000 ; Stack and heap
The supplied example also configures the MPU, and defines a 16KB memory region for the STACKHEAP. MPU regions base address must align to the size of the region, hence moving the base address above.
You will need to modify startup.s (~line 285) to make this region 1MB. This code uses macros (defined at top of the file), so this can easily be done as follows.
// Region 2 - Stack/Heap ADD r1, r1, #1 MCR p15, 0, r1, c6, c2, 0 // Set memory region number register ISB // Ensure subsequent insts execute wrt this region LDR r2, =Image$$ARM_LIB_STACKHEAP$$Base MCR p15, 0, r2, c6, c1, 0 // Set region base address register // LDR r2, =0x0 | (Region_16K << 1) | Region_Enable LDR r2, =0x0 | (Region_1M << 1) | Region_Enable MCR p15, 0, r2, c6, c1, 2 // Set region size & enable register LDR r2, =0x0 | (Full_Access << 8) | Normal_nShared | Execute_Never MCR p15, 0, r2, c6, c1, 4 // Set region access control register
I tested with Development Studio 2024.0, but I am sure this example is the same in 2019.1.
Hello Ronan,
Thanks for your suggestion and help. I'm able to run my code on Cortex-R8 in the FVP environment.
As a follow up I'm also investigating options for profiling my code on Coretx-R8. If you can share any insight/feedback on Cortex-R8 profiling, will help me a lot.
Thanks again.