I have a tight loop listed as follow. thumb-2. Using the fast model.
PC=0x700abdfe DISASS="MRRC p15,#0,r0,r1,c14"
PC=0x700abe02 DISASS="SUBS r0,r0,r2"
PC=0x700abe04 DISASS="SBC r1,r1,r3"
PC=0x700abe08 DISASS="SUBS r0,r0,r4"
PC=0x700abe0a DISASS="SBCS r1,r1,r5"
PC=0x700abe0c DISASS="BCC {pc}-0xe ; 0x700abdfe"
The target address,0x700abdfe, is not 4 byte aligned, the performance hit is huge.
The real issue is that when cpu stalls, the timer slows down too, which doesn't make sense.
"MRRC p15,#0,r0,r1,c14" reads the timer register which shouldn't matter if this loop is going slowly.
Are there any known issues regarding the timer s in the fast model?
Duplicate of:https://community.arm.com/support-forums/f/compilers-and-libraries-forum/52169/how-to-force-the-branch-target-to-be-4-byte-aligned-any-compiler-options-to-do-that-i-am-using-arm-a15