Hello,
I would like to disable the FPU on my ARM Cortex A9 CPU during the boot software execution.
But I need to employ RSA authentication to guarantee the integrity of my image partitions.
As I am trying to compile my boot software using arm-none-eabi-gcc with no FPU support, I noticed that the Xilinx xilrsa.a library may access VFP registers (FPU or NEON). See the exact errors at the bottom of my post.
However as I looked at the disassembly code, no vector instruction appears (e.g. vadd, vstr...) , and all accessed registers are with the general purpose range (0~15).
What would trigger this error then? Is it because the library has been compiled with arguments -mfpu=vfpv3 and -mfloat-abi=hard ??
Thank you
Florian
/usr/lib/gcc/arm-none-eabi/5.4.1/../../../arm-none-eabi/bin/ld: error: ../../ssbl_bsp//ps7_cortexa9_0/lib/librsa.a(SoftRSA.o) uses VFP register arguments, ssbl.elf does not /usr/lib/gcc/arm-none-eabi/5.4.1/../../../arm-none-eabi/bin/ld: failed to merge target specific data of file ../../ssbl_bsp//ps7_cortexa9_0/lib/librsa.a(SoftRSA.o) /usr/lib/gcc/arm-none-eabi/5.4.1/../../../arm-none-eabi/bin/ld: error: ../../ssbl_bsp//ps7_cortexa9_0/lib/librsa.a(SoftSHA256.o) uses VFP register arguments, ssbl.elf does not /usr/lib/gcc/arm-none-eabi/5.4.1/../../../arm-none-eabi/bin/ld: failed to merge target specific data of file ../../ssbl_bsp//ps7_cortexa9_0/lib/librsa.a(SoftSHA256.o)
Alright, my solution is that:
- the RSA library has been compiled with -mfpu=vpfv3 and -mfloat-abi=hard
- But the disassembly code does not use any VPF instruction or register
==> I must compile all the code with -mfpu=vpfv3 and -mfloat-abi=hard, but the boot assembly code does not need to enable FPU (FPEXC register).