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How to disable neon option at armv8-a

mongolee over 4 years ago

Hello,

First of all, thank you so much for all the kind and detailed answer..

I am running simulation using cortex-53 or cortex-72 model, but my model does not support the below dup instruction.

I am using gnu compiler now.. so I tried to remove simd instruction by adding + nosimd option as below code..

ARCH = armv8-a+nosimd+nofp.

However, after doing compilation I still see dut instruction, no change.. Would you let me know how can I remove dup in my code ? (maybe disable simd..)

###################
# AArch64 toolchain executables
#AS64      := $(GCC_TOOLCHAIN_AARCH64)-as
AS64 := /home/junieu/TEMP/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf/bin/aarch64-none-elf-as
#GCC64     := $(GCC_TOOLCHAIN_AARCH64)-gcc
GCC64 := /home/junieu/TEMP/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf/bin/aarch64-none-elf-gcc
#LD64      := $(GCC_TOOLCHAIN_AARCH64)-ld
LD64 := /home/junieu/TEMP/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf/bin/aarch64-none-elf-ld
#OBJCOPY64 := $(GCC_TOOLCHAIN_AARCH64)-objcopy
OBJCOPY64 := /home/junieu/TEMP/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf/bin/aarch64-none-elf-objcopy

GCC_DISASS := /home/junieu/TEMP/gcc-arm-9.2-2019.12-x86_64-aarch64-none-elf/bin/aarch64-none-elf-objdump
GCC_DISASS_OPTS := --disassemble-all -disassemble-zeros


DISASSEMBLER := $(GCC_DISASS)
DISASSEMBLER_OPTS := $(GCC_DISASS_OPTS)


################################################################################
# Processor options
################################################################################

# CPU and architecture
#CPU  = cortex-a53
CPU  = cortex-a53 #2020.05.06 JU
ARCH = armv8-a+nosimd+nofp

# FPU types
FPU_NONE      :=
FPU_V8        := -mfpu=neon-fp-armv8
#FPU_V8_CRYPTO := -mfpu=crypto-neon-fp-armv8

# Active FPU, can be overridden by tests
FPU = $(FPU_V8)
#FPU = $(FPU_NONE)


################################################################################
# Commands and command options
################################################################################

# Assembler setup
ASM32            = $(AS32)
ASM64            = $(AS64)
ifeq ($(findstring +bigend, $(PLUSARGS) ), +bigend)
ASM_OPTS_AARCH32 = -march=$(ARCH) $(FPU) --defsym BIGEND=1 -mbig-endian
ASM_OPTS_AARCH64 = -march=$(ARCH) --defsym BIGEND=1 -mbig-endian
else
ASM_OPTS_AARCH32 = -march=$(ARCH) $(FPU) --defsym EXEC_CPU=$(EXEC_CPU)
ASM_OPTS_AARCH64 = -march=$(ARCH) --defsym EXEC_CPU=$(EXEC_CPU)
endif

# C compiler setup
CC32             = $(GCC32)
CC64             = $(GCC64)
ifeq ($(findstring +bigend, $(PLUSARGS) ), +bigend)
CC_OPTS_AARCH32  = -march=$(ARCH) -mtune=$(CPU) $(FPU) -c -DGCC -falign-functions=16 -fno-common -falign-jumps=8 -falign-loops=8 -fomit-frame-pointer -funroll-loops -g -mbig-endian
CC_OPTS_AARCH64  = -march=$(ARCH) -mtune=$(CPU)        -c -DGCC -falign-functions=16 -falign-jumps=8 -falign-loops=8 -fomit-frame-pointer -funroll-loops -g -mbig-endian
else
CC_OPTS_AARCH32  = -march=$(ARCH) -mtune=$(CPU) $(FPU) -c -DGCC -falign-functions=16 -fno-common -falign-jumps=8 -falign-loops=8 -fomit-frame-pointer -funroll-loops -g
CC_OPTS_AARCH64  = -march=$(ARCH) -mtune=$(CPU)        -c -DGCC -falign-functions=16 -falign-jumps=8 -falign-loops=8 -fomit-frame-pointer -funroll-loops -g
endif