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Q: Why ARM generates undefined instruction exception but PC and instruction are both OK

yuan shao
Dear All,

I have met some problem which holds me for almost 2 weeks. I worked on some ARM926EJ-S based chip. The code sometime can run up to 2-3 days with no problem, but sometime after few hours running, ARM generated "undefined instruction" exception. I use the ICE debugger to trace the problem, the value in "lr" is good, in terms of it is within well defined code area. So I did one experiment, in the "undefined exception handler", I just simply set the PC back to the "lr", and the code can resume without any problem. In my case, I turn on the Icache and Dcache.
Does anyone have the similar experience before? or Any idea? Thanks a lot!

Ys1234
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  • Arm Employee Badge
    Note: This was originally posted on 8th March 2012 at http://forums.arm.com


    Actually I have seen two cases, one case is I-cache content is OK, the "undefined instruction handler" can simply set the PC to the lr-4, and the code continue running OK. Another case is I-cache content is wrong, [...]


    How do you find out what the I-cache content is?  Doing an LDR rn, [lr, -4] in the undef handler is going to read the data cache not the instruction cache.

    If the instruction fetch sometimes returns bad data then you might see symptoms like this -- but I'd expect more problems than just undef instructions at one location.

    Is the code that is undeffing being loaded/modified?
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  • Arm Employee Badge
    Note: This was originally posted on 8th March 2012 at http://forums.arm.com


    Actually I have seen two cases, one case is I-cache content is OK, the "undefined instruction handler" can simply set the PC to the lr-4, and the code continue running OK. Another case is I-cache content is wrong, [...]


    How do you find out what the I-cache content is?  Doing an LDR rn, [lr, -4] in the undef handler is going to read the data cache not the instruction cache.

    If the instruction fetch sometimes returns bad data then you might see symptoms like this -- but I'd expect more problems than just undef instructions at one location.

    Is the code that is undeffing being loaded/modified?
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