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Q: Why ARM generates undefined instruction exception but PC and instruction are both OK

yuan shao
Dear All,

I have met some problem which holds me for almost 2 weeks. I worked on some ARM926EJ-S based chip. The code sometime can run up to 2-3 days with no problem, but sometime after few hours running, ARM generated "undefined instruction" exception. I use the ICE debugger to trace the problem, the value in "lr" is good, in terms of it is within well defined code area. So I did one experiment, in the "undefined exception handler", I just simply set the PC back to the "lr", and the code can resume without any problem. In my case, I turn on the Icache and Dcache.
Does anyone have the similar experience before? or Any idea? Thanks a lot!

Ys1234
  • Note: This was originally posted on 8th March 2012 at http://forums.arm.com

    Hi Charlie,

    Thanks for your reply. Actually I have seen two cases, one case is I-cache content is OK, the "undefined instruction handler" can simply set the PC to the lr-4, and the code continue running OK. Another case is I-cache content is wrong, and I add Icache invalidate in the "undefined instruction handler" to force the instruction reload from the external memory when execute next time, and the code continue running OK. And the exception always happen on the same address. But the same address running OK most of the time (my program is a while(1) loop), meaning no except at all.

    Thanks.

    Ys1234


    Can you read back I-cache content when it hits the undefined exception?
    When you read the instruction pointed by LR through the debugger, it would be re-loaded from the external memory then you should see the different instruction than the one I-cache line.

    Regards,
    Charlie





  • Note: This was originally posted on 8th March 2012 at http://forums.arm.com

    Hi Scott,

    The Icache wrong is just from the behavior I see. At very beginning, in the exception handler, I only set the PC to lr-4, and let the code continue to run, and I put a counter in the handler to count how many times exception happened. In this case, I assume the exception code is fetched from I-cache for the second run. The icache size is 16K, and RR mode is used. With this handler, on one device can run 3 days with 4-5 times exception. But on another device, after few times exception, the code get stuck with the exception, seems the second time read instruction still wrong. Then I add Icache invalidate in the handler to force the second fetch is from DDR, then the second device can also run to 3 days.

    The code itself is read only, never changed.

    I am not convinced it is a SW bug. But if there is bug btw the AHB bus and DRAM controller, the symptoms could be more as you said.

    Thanks!

    Ys1234


    How do you find out what the I-cache content is?  Doing an LDR rn, [lr, -4] in the undef handler is going to read the data cache not the instruction cache.

    If the instruction fetch sometimes returns bad data then you might see symptoms like this -- but I'd expect more problems than just undef instructions at one location.

    Is the code that is undeffing being loaded/modified?
  • Note: This was originally posted on 20th March 2012 at http://forums.arm.com

    Thanks, Charlie. I will test more as you suggested.

    ys1234

    Hi YS1234,

    For checking external memory, I'd like to suggest relocation of your code to different address of external memory.
    One more thing for checking internal path or cache line fill, you could add one or two 'NOP' prior to the problematic instruction and see what's different.

    Thanks,
    Charlie
  • Note: This was originally posted on 7th March 2012 at http://forums.arm.com

    Can you read back I-cache content when it hits the undefined exception?
    When you read the instruction pointed by LR through the debugger, it would be re-loaded from the external memory then you should see the different instruction than the one I-cache line.

    Regards,
    Charlie
  • Note: This was originally posted on 19th March 2012 at http://forums.arm.com

    Hi YS1234,

    For checking external memory, I'd like to suggest relocation of your code to different address of external memory.
    One more thing for checking internal path or cache line fill, you could add one or two 'NOP' prior to the problematic instruction and see what's different.

    Thanks,
    Charlie
  • Arm Employee Badge
    Note: This was originally posted on 8th March 2012 at http://forums.arm.com


    Actually I have seen two cases, one case is I-cache content is OK, the "undefined instruction handler" can simply set the PC to the lr-4, and the code continue running OK. Another case is I-cache content is wrong, [...]


    How do you find out what the I-cache content is?  Doing an LDR rn, [lr, -4] in the undef handler is going to read the data cache not the instruction cache.

    If the instruction fetch sometimes returns bad data then you might see symptoms like this -- but I'd expect more problems than just undef instructions at one location.

    Is the code that is undeffing being loaded/modified?