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Q: Why ARM generates undefined instruction exception but PC and instruction are both OK

yuan shao
Dear All,

I have met some problem which holds me for almost 2 weeks. I worked on some ARM926EJ-S based chip. The code sometime can run up to 2-3 days with no problem, but sometime after few hours running, ARM generated "undefined instruction" exception. I use the ICE debugger to trace the problem, the value in "lr" is good, in terms of it is within well defined code area. So I did one experiment, in the "undefined exception handler", I just simply set the PC back to the "lr", and the code can resume without any problem. In my case, I turn on the Icache and Dcache.
Does anyone have the similar experience before? or Any idea? Thanks a lot!

Ys1234
Parents
  • Note: This was originally posted on 8th March 2012 at http://forums.arm.com

    Hi Scott,

    The Icache wrong is just from the behavior I see. At very beginning, in the exception handler, I only set the PC to lr-4, and let the code continue to run, and I put a counter in the handler to count how many times exception happened. In this case, I assume the exception code is fetched from I-cache for the second run. The icache size is 16K, and RR mode is used. With this handler, on one device can run 3 days with 4-5 times exception. But on another device, after few times exception, the code get stuck with the exception, seems the second time read instruction still wrong. Then I add Icache invalidate in the handler to force the second fetch is from DDR, then the second device can also run to 3 days.

    The code itself is read only, never changed.

    I am not convinced it is a SW bug. But if there is bug btw the AHB bus and DRAM controller, the symptoms could be more as you said.

    Thanks!

    Ys1234


    How do you find out what the I-cache content is?  Doing an LDR rn, [lr, -4] in the undef handler is going to read the data cache not the instruction cache.

    If the instruction fetch sometimes returns bad data then you might see symptoms like this -- but I'd expect more problems than just undef instructions at one location.

    Is the code that is undeffing being loaded/modified?
Reply
  • Note: This was originally posted on 8th March 2012 at http://forums.arm.com

    Hi Scott,

    The Icache wrong is just from the behavior I see. At very beginning, in the exception handler, I only set the PC to lr-4, and let the code continue to run, and I put a counter in the handler to count how many times exception happened. In this case, I assume the exception code is fetched from I-cache for the second run. The icache size is 16K, and RR mode is used. With this handler, on one device can run 3 days with 4-5 times exception. But on another device, after few times exception, the code get stuck with the exception, seems the second time read instruction still wrong. Then I add Icache invalidate in the handler to force the second fetch is from DDR, then the second device can also run to 3 days.

    The code itself is read only, never changed.

    I am not convinced it is a SW bug. But if there is bug btw the AHB bus and DRAM controller, the symptoms could be more as you said.

    Thanks!

    Ys1234


    How do you find out what the I-cache content is?  Doing an LDR rn, [lr, -4] in the undef handler is going to read the data cache not the instruction cache.

    If the instruction fetch sometimes returns bad data then you might see symptoms like this -- but I'd expect more problems than just undef instructions at one location.

    Is the code that is undeffing being loaded/modified?
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