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Calculating L1 hit latency and L2 hit latency

Note: This was originally posted on 16th January 2012 at http://forums.arm.com

All,

I am new here. I was interested in measuring the L1 hit latency for A15/A9. Which signals do I need to probe inside the ARM RTL to figure that out.for

1) L1 hit only
2) Also I have a scenario where I generate a L1miss and L2 hit. I need to evaluate the cache latency for l2 hit in that scenario too. Again which signals should I probe inside  each ARM CPU to figure that out.

Thanks much,

Dmax
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