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cache maintenance on cortex-a8

Jerry Fan
Note: This was originally posted on 17th November 2011 at http://forums.arm.com

[size=2]Hi ARM experts,
I am a little confused about the cache maintenance on cortex-a8. Some understanding were listed as follow, if there is any error, please correct me.

1. If a word (0x55aa for example)is written to a memory space(address A) which is write-back and write-allocate and a cache miss occurred, then [/size]
   1) if there is no clean cache line, a certain cache line will be flush to main memory and then marked as clean, then a cache line will be allocated, and we name this cache line "cache line A" and assume the          cache line size is 32bytes.
   2) 32 bytes data in the destination memory  will be filled to the cache line A .
   3) 0x55aa will be written to cache line A and the cache line A will marked as "dirty"
2. If a word (0x55aa for example)is written to a memory space (address A) which is write-though and no-write-allocate and a cache miss occurred, then
   1)0x55aa is write to the main memory directly.
   2)There is no "copy" of  (address A) in the cache.
   3) If the address A was read, 32 bytes data will filled into the cache. If there is not clean cache, a certain cache line will be flush to main memory and then marked as clean.
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  • Arm Employee Badge
    Note: This was originally posted on 21st November 2011 at http://forums.arm.com

    The only bit I would query is:

    " If there is not clean cache, a certain cache line will be flush to main memory and then marked as clean."

    AFIK, the ARM processors do no favour clean cache lines over dirty lines.  The processor selects which line to replace first,  and then checks to see whether it is dirty or not.

    Some processors will favour invalid lines over valid.
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  • Arm Employee Badge
    Note: This was originally posted on 21st November 2011 at http://forums.arm.com

    The only bit I would query is:

    " If there is not clean cache, a certain cache line will be flush to main memory and then marked as clean."

    AFIK, the ARM processors do no favour clean cache lines over dirty lines.  The processor selects which line to replace first,  and then checks to see whether it is dirty or not.

    Some processors will favour invalid lines over valid.
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