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cache maintenance on cortex-a8

Jerry Fan
Note: This was originally posted on 17th November 2011 at http://forums.arm.com

[size=2]Hi ARM experts,
I am a little confused about the cache maintenance on cortex-a8. Some understanding were listed as follow, if there is any error, please correct me.

1. If a word (0x55aa for example)is written to a memory space(address A) which is write-back and write-allocate and a cache miss occurred, then [/size]
   1) if there is no clean cache line, a certain cache line will be flush to main memory and then marked as clean, then a cache line will be allocated, and we name this cache line "cache line A" and assume the          cache line size is 32bytes.
   2) 32 bytes data in the destination memory  will be filled to the cache line A .
   3) 0x55aa will be written to cache line A and the cache line A will marked as "dirty"
2. If a word (0x55aa for example)is written to a memory space (address A) which is write-though and no-write-allocate and a cache miss occurred, then
   1)0x55aa is write to the main memory directly.
   2)There is no "copy" of  (address A) in the cache.
   3) If the address A was read, 32 bytes data will filled into the cache. If there is not clean cache, a certain cache line will be flush to main memory and then marked as clean.
  • Note: This was originally posted on 21st November 2011 at http://forums.arm.com

    Hi ARM experts,
    Please help me figure this out. Any feedback is very appreciated.

    B.R.
    Jerry
  • Note: This was originally posted on 22nd November 2011 at http://forums.arm.com

    Hi ttfn,
    Thanks for your reply.
    AFIK, the ARM processors do no favour clean cache lines over dirty lines. The processor selects which line to replace first, and then checks to see whether it is dirty or not.
    [Jerry]So, if there 's no clean line in the cache, how ARM processors decide which line should be cleaned?
       if clean lines and dirty lines both exist  in the cache, how ARM processors decide which line should be cleaned?
    Where I can get the doc about this?

    Some processors will favour invalid lines over valid.

    B.R
    Jerry
  • Note: This was originally posted on 23rd November 2011 at http://forums.arm.com

    Thanks for your reply , Lilywild.
    But how to determine a certern  cpu(cortex-a8 arch) implemented the  Predictable strategy or not?
    For memory copy, which  strategy will be better?


    Best Regards
    Jerry
  • Arm Employee Badge
    Note: This was originally posted on 21st November 2011 at http://forums.arm.com

    The only bit I would query is:

    " If there is not clean cache, a certain cache line will be flush to main memory and then marked as clean."

    AFIK, the ARM processors do no favour clean cache lines over dirty lines.  The processor selects which line to replace first,  and then checks to see whether it is dirty or not.

    Some processors will favour invalid lines over valid.
  • Arm Employee Badge
    Note: This was originally posted on 23rd November 2011 at http://forums.arm.com

    Caches are complex, and it is mostly a game of statistics. The cache / the algorithms it uses are designed to give reliable average performance, irrespective of use case. Pseudo-random policies are generally chosen as while not as good as more specific strategies for some use cases, they avoid absolutely pathologically bad corner cases too...

    So in short, as long as caches are turned on, I wouldn't worry about it. You'd be far better off working out how to avoid the copy completely, if you can ...

    Iso
  • Note: This was originally posted on 22nd November 2011 at http://forums.arm.com

    -> [Jerry]So, if there 's no clean line in the cache, how ARM processors decide which line should be cleaned?
    ->   if clean lines and dirty lines both exist  in the cache, how ARM processors decide which line should be cleaned?
    ->    Where I can get the doc about this?

    "selects which line to replace first" means processor first select the line to replace with a pre-defined strategy, and then clean(flush+invalidate) the selected line if it's dirty.

    RR(bit 14) of System Control Register (SCTLR) of ARMv7 TRM describes that:

    0 - Normal replacement strategy, for example, random replacement
    1 - Predictable strategy, for example, round-robin replacement.
  • Note: This was originally posted on 24th November 2011 at http://forums.arm.com


    Caches are complex, and it is mostly a game of statistics. The cache / the algorithms it uses are designed to give reliable average performance, irrespective of use case. Pseudo-random policies are generally chosen as while not as good as more specific strategies for some use cases, they avoid absolutely pathologically bad corner cases too...

    So in short, as long as caches are turned on, I wouldn't worry about it. You'd be far better off working out how to avoid the copy completely, if you can ...

    Iso


    100% agree with you.