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Synchronization in SMP-system WFE/SEV DMB/DSB

Soren Brinkmann
Note: This was originally posted on 31st October 2011 at http://forums.arm.com

Hi, I'm trying to synchronize a Cortex-A9 MPCore in SMP mode, but am failing this far. I tried to figure out how to use the barriers correctly, but apparently I'm missing something. The code looks basically like this:

CPU0:
   str   r0, [ADDR]
   dsb
   sev

CPU1:
   wfe
   dsb    @ I added this later, doesn't seem to have any effect
   ldr   r0, [ADDR]


The problem is, CPU1 reads stale data (at least I consider it stale). I'm pretty sure it's some coherency problem, since the code works as expected with caches disabled.
I already checked:
- the MMU is enabled
- SMP bit is set in aux-ctrl
- I'm accessing fully-cacheable memory
- The SCU reports two CPUs taking part in coherent SMP.

Any hints are appreciated.
Parents
  • Note: This was originally posted on 1st November 2011 at http://forums.arm.com

    Thanks for the answer.
    I was aware that wfe/sev are not the primary constructs for synchronization, but I thought it might work in my pretty small project and I could avoid locks.
    But it appears you're right. The second CPU just runs over the WFE instruction. I don't know which event occurs, but it's not the SEV.

    So I'll use locks and a valid flag. That should work without optimistic assumptions on what events might occur.
Reply
  • Note: This was originally posted on 1st November 2011 at http://forums.arm.com

    Thanks for the answer.
    I was aware that wfe/sev are not the primary constructs for synchronization, but I thought it might work in my pretty small project and I could avoid locks.
    But it appears you're right. The second CPU just runs over the WFE instruction. I don't know which event occurs, but it's not the SEV.

    So I'll use locks and a valid flag. That should work without optimistic assumptions on what events might occur.
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