• Locked Locked
  • Replies 4 replies
  • Subscribers 119 subscribers
  • Views 4885 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Synchronization in SMP-system WFE/SEV DMB/DSB

Soren Brinkmann
Note: This was originally posted on 31st October 2011 at http://forums.arm.com

Hi, I'm trying to synchronize a Cortex-A9 MPCore in SMP mode, but am failing this far. I tried to figure out how to use the barriers correctly, but apparently I'm missing something. The code looks basically like this:

CPU0:
   str   r0, [ADDR]
   dsb
   sev

CPU1:
   wfe
   dsb    @ I added this later, doesn't seem to have any effect
   ldr   r0, [ADDR]


The problem is, CPU1 reads stale data (at least I consider it stale). I'm pretty sure it's some coherency problem, since the code works as expected with caches disabled.
I already checked:
- the MMU is enabled
- SMP bit is set in aux-ctrl
- I'm accessing fully-cacheable memory
- The SCU reports two CPUs taking part in coherent SMP.

Any hints are appreciated.
  • Note: This was originally posted on 31st October 2011 at http://forums.arm.com

    Yes, both CPUs are pointed to the same translation table. I use sections which are configured as shareable, write-back/write-allocate.
  • Note: This was originally posted on 1st November 2011 at http://forums.arm.com

    Thanks for the answer.
    I was aware that wfe/sev are not the primary constructs for synchronization, but I thought it might work in my pretty small project and I could avoid locks.
    But it appears you're right. The second CPU just runs over the WFE instruction. I don't know which event occurs, but it's not the SEV.

    So I'll use locks and a valid flag. That should work without optimistic assumptions on what events might occur.
  • Arm Employee Badge
    Note: This was originally posted on 1st November 2011 at http://forums.arm.com

    A couple of thoughts...

    SEV/WFE are not intended for synchronisation - but for power management.  Because of the way WFE is defined, there is no guarantee that the CPU1 will only awake when CPU0 executes SEV.  It could wake at time for any number of reasons.  Usually examples show SEV/WFE as a form of simple power management in a spin-lock.  Something like:

    lock_spin_lock  (assume addr in r0)
      LDREX    r1, [r0]
      CMP      r1, #UNLOCKED
      WFENE                                 ; If not unlocked go to sleep
      BNE      lock_spin_lock   ; on waking, re-check the spin-lock
      ...

    It's the spin-lcok that provides the synchronisation, not the WFE.  The WFE just is a way of saving power while you wait for the resource to become free.


    Have you looked at the the sMP boot example on ARM's website? 

    Depending on what you're trying to achieve, you could try polling instead. Using a flag, or a SGI.
  • Arm Employee Badge
    Note: This was originally posted on 31st October 2011 at http://forums.arm.com

    Are both sets of MMU tables which map that physical address range setup as "shared"?