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Interrupt not seen by M0 core

John Mount
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Note: This was originally posted on 13th October 2011 at http://forums.arm.com

I am sending an interrupt to the M0 from another processor.   In the NVIC registers I can see the interrupt pending, and I also can see that the interrupt in question is enabled. The firmware never see's the interrupt.   There must be another level of interrupt enable that I have missed.    Any suggestions?    I attached my vector table.   I am asserting general interrupt 0.   
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    Note: This was originally posted on 17th October 2011 at http://forums.arm.com

    Hi John,

    The most likely cause is that the processor has not been reset after the program memory updated.

    When the emulator starts, the program memory might be invalid and the core enters hardfault, and then lockup if another fault occurred inside hardfault handler.  After the program is updated, you might have changed the PC value and SP value, but not resetting the processor before starting the program execution.  In this case, the priority in the NVIC still think that it is in hard fault (priority level -1) and therefore does not accept interrupts.

    Also, please check the generated program image (disassembled listing / hex / binary).  I know that you have attached the vector table source code, but whether the vector table is placed correctly in the compiled image is a slightly different question.

    Which development tool chain do you use?

    Also, as you are using Cadence Palladium, I guess your company is a ARM customer and maybe you are entitle to ARM support. In such case it might be useful if you can contact ARM support directly. If needed, our FAE can visit you and might help identify issues in your system setup.

    regards,
    Joseph
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  • Offline
    Note: This was originally posted on 17th October 2011 at http://forums.arm.com

    Hi John,

    The most likely cause is that the processor has not been reset after the program memory updated.

    When the emulator starts, the program memory might be invalid and the core enters hardfault, and then lockup if another fault occurred inside hardfault handler.  After the program is updated, you might have changed the PC value and SP value, but not resetting the processor before starting the program execution.  In this case, the priority in the NVIC still think that it is in hard fault (priority level -1) and therefore does not accept interrupts.

    Also, please check the generated program image (disassembled listing / hex / binary).  I know that you have attached the vector table source code, but whether the vector table is placed correctly in the compiled image is a slightly different question.

    Which development tool chain do you use?

    Also, as you are using Cadence Palladium, I guess your company is a ARM customer and maybe you are entitle to ARM support. In such case it might be useful if you can contact ARM support directly. If needed, our FAE can visit you and might help identify issues in your system setup.

    regards,
    Joseph
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