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Interrupt not seen by M0 core

John Mount
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Note: This was originally posted on 13th October 2011 at http://forums.arm.com

I am sending an interrupt to the M0 from another processor.   In the NVIC registers I can see the interrupt pending, and I also can see that the interrupt in question is enabled. The firmware never see's the interrupt.   There must be another level of interrupt enable that I have missed.    Any suggestions?    I attached my vector table.   I am asserting general interrupt 0.   
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    Note: This was originally posted on 14th October 2011 at http://forums.arm.com

    Hi John,

    What type of test environment you are using?
    - microcontroller / silicon?
    - FPGA?
    - Verilog simulation?

    A few things to check:
    - value of PRIMASK (if set, it disable all interrupts)
    - value of IPSR (if it is already running another interrupt, then the current priority level might be higher or same as the interrupt).
    - what happen with the program? Does it still running, or does it hangs/crashed when the interrupt take place? Could you check if the vector table is set correctly in the compiled program image?

    regards,
    Joseph
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  • Offline
    Note: This was originally posted on 14th October 2011 at http://forums.arm.com

    Hi John,

    What type of test environment you are using?
    - microcontroller / silicon?
    - FPGA?
    - Verilog simulation?

    A few things to check:
    - value of PRIMASK (if set, it disable all interrupts)
    - value of IPSR (if it is already running another interrupt, then the current priority level might be higher or same as the interrupt).
    - what happen with the program? Does it still running, or does it hangs/crashed when the interrupt take place? Could you check if the vector table is set correctly in the compiled program image?

    regards,
    Joseph
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