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AXI transaction when ldm/stm instruction used on  cortex-a9

Jerry Fan
Note: This was originally posted on 15th September 2011 at http://forums.arm.com

HI, ARM experts

I used ldm/stm instruction to copy(read-write) memory with caches disabled. The code is listed as:
int memcpy_8_regs(uint32_t * dst, uint32_t * src, uint32_t len)
{
    asm volatile ("stmfd   sp!, {r3-r10}\n");
    while(len){
        asm volatile ("ldmia   r1!, {r3-r10}\n");
        asm volatile ("stmia   r0!, {r3-r10}\n");
        len -= 32;
    }
    asm volatile ("ldmfd  sp!, {r3-r10}\n");

    return 0;
}
[font="Arial"]The code was run in a simulation enviroment and the operation of arm core can be observed.
The arm core issued a axi transaction with 16(bits) * 4(length) for write access, while a  32(bits) * 8(length) transaction for read access. It is kind of werid. Why not a 32(bits) * 8(length) transaction can be issued to get a maximum throughput? The limitation is because of the cortex-a9 arch?

BR
Jerry

[/font]


Parents
  • Note: This was originally posted on 15th September 2011 at http://forums.arm.com


    [font="Arial"]The code was run in a simulation enviroment and the operation of arm core can be observed.
    The arm core issued a axi transaction with 16(bits) * 4(length) for write access, while a  32(bits) * 8(length) transaction for read access. It is kind of werid. Why not a 32(bits) * 8(length) transaction can be issued to get a maximum throughput? The limitation is because of the cortex-a9 arch?
    [/font]

    Are you sure about the write access? That'd be the content of only two registers. Depending on the memory type of the destination pointer I'd have expected 64(bits) * 4 (length) due to store merging. As far as the reads are concerned, you may also get 64 * 4 bursts, if the addresses are 8 byte aligned.

    Regards
    Marcus
Reply
  • Note: This was originally posted on 15th September 2011 at http://forums.arm.com


    [font="Arial"]The code was run in a simulation enviroment and the operation of arm core can be observed.
    The arm core issued a axi transaction with 16(bits) * 4(length) for write access, while a  32(bits) * 8(length) transaction for read access. It is kind of werid. Why not a 32(bits) * 8(length) transaction can be issued to get a maximum throughput? The limitation is because of the cortex-a9 arch?
    [/font]

    Are you sure about the write access? That'd be the content of only two registers. Depending on the memory type of the destination pointer I'd have expected 64(bits) * 4 (length) due to store merging. As far as the reads are concerned, you may also get 64 * 4 bursts, if the addresses are 8 byte aligned.

    Regards
    Marcus
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