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Boot ROM Code for ARM Cortex A9 MP Core SoC

tushark tushark
Note: This was originally posted on 5th August 2011 at http://forums.arm.com

Hi,

I am working on ARM Cortex A9 MP Core SoC. As a part of software development, I need to understand how booting takes place in case ARM Cortex A9 considering the reset vector. I wanted to know more about the Boot ROM code which could be part of SoC. Can I get details / documentation / reference code about the Boot ROM code for ARM Cortex A9? Also I would like to know what are the steps involved in general booting sequence right from the RESET/Power ON till it loads the kernel.

Thanks & Regards,
TK
  • Note: This was originally posted on 8th August 2011 at http://forums.arm.com

    Thanks Vaibhav for the information.
    I have one more question related to booting. As mentioned the execution of instructions after rest will start from address 0 or 0xFFFF0000. So If I am having NOR flash in my system, then do I need to map NOR flash to reset vector address? As NOR supports XIP, so all the initialization code should be placed in NOR at  address 0 or 0xFFFF0000 in assembly code. Is this understanding correct?

    Thanks,
    Tushark
  • Note: This was originally posted on 6th August 2011 at http://forums.arm.com

    The ARM Programmer guide has some notes on booting a bare-metal system (i.e. Code to be run immediately after the core comes out of reset and without the use of an operating system)

    To re-iterate;


    When the processor has been reset, it will commence execution at the location of the reset vector
    within the exception vector table (at either address 0 or 0xFFFF0000). The reset handler code
    will need to do some, or all of the following:
    "¢ In a multi-processor system, put non-primary processors to sleep
    "¢ Initialize exception vectors
    "¢ Initialize the memory system, including the MMU
    "¢ Initialize processor mode stacks and registers
    "¢ Initialize variables required by C
    "¢ Initialize any critical I/O devices
    "¢ Perform any necessary initialization of NEON/VFP
    "¢ Enable interrupts
    "¢ Change processor mode and/or state
    "¢ Handle any set-up required for the Secure world
    "¢ Call the main() application

    - Vaibhav
  • Note: This was originally posted on 9th August 2011 at http://forums.arm.com


    Thanks Vaibhav for the information.
    I have one more question related to booting. As mentioned the execution of instructions after rest will start from address 0 or 0xFFFF0000. So If I am having NOR flash in my system, then do I need to map NOR flash to reset vector address? As NOR supports XIP, so all the initialization code should be placed in NOR at  address 0 or 0xFFFF0000 in assembly code. Is this understanding correct?

    Thanks,
    Tushark


    Yes, you need to map the Flash to reset vector address. Your NFlash(NOR/NAND) may need to be configured to fetch instruction at address 0. Regarding choosing the higher address or not, it is upto the memory map. The memory map address 0x00000000 is reserved for the vector table, a set of 32-bit words. On some processors the vector table can be optionally located at a higher address in memory (starting at the offset 0xffff0000). Operating systems such as Linux and Microsoft's embedded products can take advantage of this feature
  • Note: This was originally posted on 24th August 2011 at http://forums.arm.com

    My understanding is that some part of it is implementation defined. As your shared .pdf also reflects that secondary code jumps to the code once it is released from primary CPU. I can visualize that once released, the secondary CPUs will (after some further local initialization) enter _sec_processor_idle () where they are ready to receive job/tasks to run. You can consider this idle() as a lowest priority thread and acting as a placeholder for when there is nothing to run on that CPU.



    Hi,

    Iam using OMAP4430 panda board for my project development. As a part of  ROM code execution (in ARMCortex A9 MP Core) core-'0' will do the system  initialization, stack setup and boot the OS. core-'1' will be waiting  for SEV flag, which is SET by core-'0' booted OS. Then core-'1' will  jump to address mentioned in AUXCOREBOOT1 register.Let me know what  is the default address that core-'1' will jump and start its execution.  Kindly refer attachment to see the ROM code execution sequence.

    Regards,
    Karthi



  • Note: This was originally posted on 24th August 2011 at http://forums.arm.com

    Hi,

    Iam using OMAP4430 panda board for my project development. As a part of  ROM code execution (in ARMCortex A9 MP Core) core-'0' will do the system  initialization, stack setup and boot the OS. core-'1' will be waiting  for SEV flag, which is SET by core-'0' booted OS. Then core-'1' will  jump to address mentioned in AUXCOREBOOT1 register.Let me know what  is the default address that core-'1' will jump and start its execution.  Kindly refer attachment to see the ROM code execution sequence.

    Regards,
    Karthi



    Yes, you need to map the Flash to reset vector address. Your NFlash(NOR/NAND) may need to be configured to fetch instruction at address 0. Regarding choosing the higher address or not, it is upto the memory map. The memory map address 0x00000000 is reserved for the vector table, a set of 32-bit words. On some processors the vector table can be optionally located at a higher address in memory (starting at the offset 0xffff0000). Operating systems such as Linux and Microsoft's embedded products can take advantage of this feature
  • Note: This was originally posted on 5th September 2011 at http://forums.arm.com

    Hi,

    Iam using OMAP4430 Panda Board for my project development. I like to know whether each core (ARMCortex A9 dual Core) has its own MMU. If both the core's shares the same MMU how the synchronization is done.

    Regards,
    Karthi
  • Arm Employee Badge
    Note: This was originally posted on 5th September 2011 at http://forums.arm.com

    Each core does have its own MMU.  However, as the page tables are in memory, there is nothing to stop them sharing one set.
  • Note: This was originally posted on 16th April 2013 at http://forums.arm.com

    Hi TK,

    Do you find the Boot ROM source code of ARM Cortex A9 MP Core soc finally? Thanks!


    Hi,

    I am working on ARM Cortex A9 MP Core SoC. As a part of software development, I need to understand how booting takes place in case ARM Cortex A9 considering the reset vector. I wanted to know more about the Boot ROM code which could be part of SoC. Can I get details / documentation / reference code about the Boot ROM code for ARM Cortex A9? Also I would like to know what are the steps involved in general booting sequence right from the RESET/Power ON till it loads the kernel.

    Thanks & Regards,
    TK