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Fast Model: Best way to model unaligned multiple register read/write

HonSiong

I am looking for a good method to implement multiple unaligned register access using LISA+ in Fast Model. Can you recommend a good way to do this?

For example, below are the register declaration:
REGISTER { reg_number(0x0000), bitwidth(16), reset_value(0x3836) } REG16_000;  //address 0x00
REGISTER { reg_number(0x0002), bitwidth(8),  reset_value(0x1)    } REG8_002;  //address 0x02
REGISTER { reg_number(0x0003), bitwidth(8),  reset_value(0x0)    } REG8_003;  //address 0x03

And in the application we should be able to perform the following:
*((uint16_t *)0x20000000) = 0xAAAA;        //write to REG16_000
*((uint32_t *)0x20000000) = 0xAAAABBCC;     //write to REG16_000, REG8_002, REG8_003
*((uint8_t *)0x20000001) = 0xAA;            //write to second byte of REG16_000 only

I am relatively new to LISA and Fast Model. And all the examples in the shows aligned access to single registers (ie: access to single register at aligned address).

Thanks in advance

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  • 0 Arm Employee Badge in reply to HonSiong

    You can find an example of how to implement a simple register bank in the SimplePVbusMaster component.

    The access to the register will be done via the device port of the PVBusSlave component, and you can deal with different access sizes at this point with the granularity you need.

    internal slave port<PVDevice> device
  {
    behavior read(pv::ReadTransaction tx):pv::Tx_Result
    {
    // implement the desired register read accesses here
    // treating your registers as normal variables
    }
    ...
  }

    I hope that helps,

    Simon

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  • 0 Arm Employee Badge in reply to HonSiong

    You can find an example of how to implement a simple register bank in the SimplePVbusMaster component.

    The access to the register will be done via the device port of the PVBusSlave component, and you can deal with different access sizes at this point with the granularity you need.

    internal slave port<PVDevice> device
  {
    behavior read(pv::ReadTransaction tx):pv::Tx_Result
    {
    // implement the desired register read accesses here
    // treating your registers as normal variables
    }
    ...
  }

    I hope that helps,

    Simon

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