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pipeline result register write.

Etienne SOBOLE
Note: This was originally posted on 13th January 2011 at http://forums.arm.com

Hi.

I'm trying to develop a small program to count the cycle of a program.
I found an interresting case.

As you know 2 instructions can not execute in the same cycle if the destination registrer is the same.
It's sound logic, but in fact due to pipeline step, this is not as logic at it should be.

For example the next code should work

mov  r0, #15
add  r0, r0, #15


The MOV will write r0 in E1
The ADD will write r0 in E2
So there is no good reason to not start instruction execution in the same cycle

An opposite case is the next one


mul  r0, r1, r2
nop
add  r0, r5, r6
add  r0, r6, r7


The mul will execute in pipe 0 and write is result in E5
The 2 ADD will execute in separate pipeline 0 and pipeline 1 (due to the same destination regsiter). But they both have to wait for r0.
So finally they will execute exactly in the same cycle and should write their result in the same cycle.

So finally my question (because there is always a question):
What mean issued in this sentence
"Instructions with the same destination cannot be issued in the same cycle"

Does it mean the started cycle or the writing result cycle ?

Etienne
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