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pipeline result register write.

Etienne SOBOLE
Note: This was originally posted on 13th January 2011 at http://forums.arm.com

Hi.

I'm trying to develop a small program to count the cycle of a program.
I found an interresting case.

As you know 2 instructions can not execute in the same cycle if the destination registrer is the same.
It's sound logic, but in fact due to pipeline step, this is not as logic at it should be.

For example the next code should work

mov  r0, #15
add  r0, r0, #15


The MOV will write r0 in E1
The ADD will write r0 in E2
So there is no good reason to not start instruction execution in the same cycle

An opposite case is the next one


mul  r0, r1, r2
nop
add  r0, r5, r6
add  r0, r6, r7


The mul will execute in pipe 0 and write is result in E5
The 2 ADD will execute in separate pipeline 0 and pipeline 1 (due to the same destination regsiter). But they both have to wait for r0.
So finally they will execute exactly in the same cycle and should write their result in the same cycle.

So finally my question (because there is always a question):
What mean issued in this sentence
"Instructions with the same destination cannot be issued in the same cycle"

Does it mean the started cycle or the writing result cycle ?

Etienne
  • Note: This was originally posted on 16th January 2011 at http://forums.arm.com

    hi

    issuing means the starting cycle. As for the two examples given, both are right: issuing the dependent instructions is done according to a scoreboard (not traditional) in the decode stages. The scoreboard counts the cycles after which each of the two instructions will be writing and issue correspondingly. Because in the 1st example MOV writes after 2cycles (E0-E1) while ADD after 3 cycles => can be issued together. In the 2nd example both instructions will write  together after 3 cycles and will no therefore be issued from the decode at the same cycle (as dual).

    But i have a question for you: when they say that the MOV e.g. will write at E1, they mean that the answer will be available for forward at E1 and wait till E5 to write into the reg file of is it that it will write at E1 into the reg file??
  • Note: This was originally posted on 29th January 2011 at http://forums.arm.com

    hello Etienne

    sorry for replying late but i was so busy the last period

    finally i got answers for our questions

    as for my previous reply, i discovered that the scoreboard in the decode pipeline checks for RAW hazards only and not WAW hazards.

    However, the issue logic includes cross checking of the instructions to be dual issued. The cross checking allows detection of RAW and WAW hazards between the two instructions. Note that RAW hazards are always evaluated in terms of when needed and when available.
    If the cross checking provided that RAW or WAW hazard occurs: dual issue will NOT occur, and this what happened in the 1st example where two cycles were required.   then why is it so when dest reg can be available before E5? this is because instructions should commit  in order to ensure avoiding WAW hazards among instructions and to handle exceptions correctly. So the two instructions if issued together, will be writing into the same register together: not allowed (through adding any logic for prioritization) by cortex A8

    And answering my qstn: it turned to be that all instructions will write-back into the register file in E5.

    (yes my info is from an official document about the cortex :)  no assumptions unless stated :) )

    and by the way in your first post,be careful that the add will not wait for mult to write in E5 . this is because a new instruction with a RAW hazard with an older one can issue (get into the Execute pipeline) as soon as the req reg is available by forwarding.

    So issuing is sending instructions out from decode pipeline into execute pipeline 

    Regards
  • Note: This was originally posted on 17th January 2011 at http://forums.arm.com

    Hi.

    Are you sure about what you said or do you soppuse it's work like this.
    Do you have found your information somewhere in the cortex documentation ??)

    Because I've tested and


    mov  r0, #15
    add  r0, r0, #15


    Take finally 2 cycles on the cortex A8 (even if this is not really logical).

    For the second code, it's a little bit more complexe to test. I do not have correct result for the moment.

    To reply your question :
    The result cycle indicate the cycle where the register can be used by other instructions.
    I don't know if the data is effectively written to register file or if it have to wait for the writeback cycle.
    But I don't really understand the interest of writeback cycle while the regsiter can be used anyway.

    The doc just say that sometime the register in not available before the writeback cycle, but most of the case it is available sooner.

    Etienne
  • Arm Employee Badge
    Note: This was originally posted on 13th January 2011 at http://forums.arm.com

    As you know 2 instructions can not execute in the same cycle if the destination registrer is the same.


    This is not strictly true on all cores.